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Intermediate Bus Architecture: A Space‑Saving Power Design Technique

Intermediate Bus Architecture: A Space‑Saving Power Design Technique

Power electronics has evolved from mercury‑arc rectifiers to modern IGBTs, driving demand for smaller, cost‑effective systems in clean energy, EVs, and data centers. One emerging solution is the Intermediate Bus Converter (IBC), which can shrink PCB footprints while keeping efficiency high.

While the Distributed Power Architecture (DPA) remains the industry standard for point‑of‑load (POL) designs, the Intermediate Bus Architecture (IBA) offers a two‑stage approach that lets designers use low‑voltage, low‑inductance POL converters. This reduces inductor size, cuts cost, and can halve the total solution area.

Intermediate Bus Architecture: A Space‑Saving Power Design Technique

Figure 1. One‑stage traditional DPA vs. 2‑stage IBA

The trade‑offs between IBA and DPA depend largely on the number of power rails:

IBC ArchitectureDPA Architecture
CostLower cost from smaller inductors and POL convertersHigher cost due to high‑voltage process and larger inductance
EfficiencyLower system efficiency from the first conversion stageHigher efficiency without an intermediate stage
Solution SizeSmaller total footprintLarger footprint
Power DensityHigher power densityLower power density
# of RailsIdeal for 3+ output railsIdeal for <3 output rails

To illustrate the approach, Intel’s EC2650QI 12‑to‑6 V Intermediate Bus Converter and Enpirion PowerSoCs are used as reference designs.

SpecificationsFeatures
VIN: 8 – 13.2 VUp to 94 % efficiency
VOUT: VIN / 20.9 mm height
6 A continuous output current36 W output power per bus converter
150 mm² solution sizeParallel capable (up to four for 144 W total)

Multi‑Stage Power Conversion: Reducing PCB Size

In a single‑stage 12 V → 3.3 V conversion, the downstream DC‑DC module must tolerate at least 20 V, necessitating a high‑voltage process and a larger inductor. Switching at a higher frequency to keep ripple low increases losses, further inflating size.

A two‑stage IBA first steps 12 V down to 6 V, allowing the next POL module to run on a 10 V process. This reduces inductor size and cost, and improves thermal performance.

Managing the Two‑Stage Efficiency Penalty

System efficiency hinges on the IBC’s performance. Intel’s EC2650QI achieves up to 94 % efficiency via a switched‑capacitor topology. For example:

Although the two‑stage path drops efficiency slightly, the space savings can outweigh the loss. Designers can further tune the design by selecting low‑current IBCs, using larger POL converters, or hybridizing small and large POLs.

When to Adopt IBA?

IBA is most advantageous when you need to accommodate three or more rails while keeping PCB area and cost low. A typical case study shows:

1‑Stage with Large POLs2‑Stage with Small POLs
Efficiency: ~87 %Efficiency: ~84 %
Total solution size: 800 mm²Total solution size: 390 mm²

Replacing two small POLs with larger, more efficient EN6362QIs raises efficiency to ~85 % while keeping the footprint 26 % smaller than DPA.

Customizing IBA for Your Design

IBA provides flexibility: use high‑efficiency IBCs, parallel devices, and tailored POL selections to balance size, cost, and performance. Intel’s EC2650QI can be paralleled up to four units, delivering 144 W at only 150 mm² per device.

Additional Resources

Industry Articles provide expert insights and are subject to editorial guidelines.

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