Arm Introduces Custom Instruction Support for Cortex‑M Cores, Expanding Flexibility

SAN JOSE, Calif. — In a landmark announcement at Arm TechCon, Arm CEO Simon Segars revealed that the company will now permit licensees to embed custom instructions within its Cortex‑M cores, marking a significant shift from its historically rigid instruction set architecture (ISA).

After decades of maintaining a tightly controlled ISA, Arm is opening up its architecture to allow users to create specialized instructions that accelerate niche workloads.

While other intellectual‑property firms—such as Tensilica (now part of Cadence), ARC (now part of Synopsys), and the legacy MIPS ISA—have long offered user‑defined instructions, Arm had resisted this trend to preserve a consistent programming model.

With the rise of the open‑source RISC‑V ISA and its configurability, Arm has finally relented, addressing two key concerns that have driven customers toward RISC‑V: flexibility and cost.

First on Cortex‑M, then on Cortex‑R, Arm will release customizable instruction support for the Cortex‑M33, the first part to receive this capability. Future Cortex‑M cores will also support it.

Arm will provide this feature at no additional cost for the Cortex‑M33. According to Arm Fellow Peter Greenhalgh, the company plans to extend custom‑instruction support to Cortex‑R real‑time cores—and may eventually add it to Cortex‑A application processors.

Arm Fellow Peter Greenhalgh at Arm TechCon 2019 (Image: Kevin Krewell)

Custom instructions on Cortex‑R can dramatically speed real‑time control applications by embedding specialized operations for compute‑heavy or data‑movement tasks. Whether and when Arm will bring this capability to Cortex‑A cores, used in smartphones and servers, remains uncertain.

Arm’s toolchain now supports these user instructions in the Armv8‑M ISA while preserving the reliability and verification standards the ecosystem expects. The new capability is also fully compatible with Arm TrustZone, allowing the security framework to monitor custom operations.

Although Arm entered the custom‑instruction arena later than its peers, the move responds to longstanding customer demand. Even a single specialized instruction can deliver measurable gains in performance, reducing clock cycles and energy consumption—albeit with modest die‑area and design‑time trade‑offs.

Custom instructions will be interleaved with standard Arm opcodes. To avoid software fragmentation and maintain a coherent development environment, Arm recommends that customers employ them primarily within library functions.

Arm Custom Instructions for Armv8‑M configuration space (Source: Arm's white paper)

Initial use cases targeted by Arm include storage controllers and modems. The custom‑instruction feature will be available as a free upgrade for the Cortex‑M33 in 2020.

For Cortex‑A cores, Arm is still several years away from offering custom instructions but is developing new instructions and security extensions for the forthcoming Matterhorn core, the successor to Hercules. Matterhorn is slated to accelerate matrix multiplication—critical for neural‑network inference—with a projected 10× improvement in General Matrix Multiply (GEMM) performance.

In addition to performance gains, Matterhorn will introduce pointer‑authorization, branch‑target identifiers, and memory‑tagging extensions, paving the way for Platform Security Architecture (PSA) EL2 compliance.

Earlier this year, Arm unveiled its Flexible Access licensing program, slashing upfront costs. Under the program, customers pay only $75,000 per year for a single chip and $200,000 for unlimited chips, eliminating the need for a full licensing agreement until the design is taped out.

This flexible pricing strategy lowers the financial barrier for developers and signals Arm’s competitive response to RISC‑V.

Arm is also reshaping its corporate culture to foster deeper collaboration. For example, the company has opened governance of the open‑source Mbed OS to silicon partners—including Analog Devices, Cypress, Maxim Integrated, Nuvoton, NXP, Renesas, Realtek, Samsung, Silicon Labs, and u‑blox—allowing them to influence future roadmap decisions.

Arm’s IP has already shipped on 150 billion chips and the company projects that number will double in the next two years, underscoring its critical role in the global semiconductor ecosystem.