RISC‑V International and CHIPS Alliance Launch OmniXtend Working Group to Enhance Cache Coherency Standards

RISC‑V International and CHIPS Alliance have announced a joint collaboration to update the OmniXtend Cache Coherency specification and protocol, while building out developer tools to support the new standard.

A new OmniXtend working group has been formed to create an open, cache‑coherent, unified memory standard for multicore compute architectures. OmniXtend is a fully open networking protocol that exchanges coherence messages directly with processor caches, memory controllers and a variety of accelerators, providing an efficient way to attach new accelerators, storage and memory devices to RISC‑V systems‑on‑chip (SoCs). It can also enable multi‑socket RISC‑V systems.

The group will update the OmniXtend specification and protocol, develop architectural simulation models, deliver a reference register‑transfer‑level (RTL) implementation, and construct a verification workbench. These tools will simplify designers’ use of OmniXtend for data‑centric applications.

“As RISC‑V International develops implementation‑independent specifications and ecosystem components, it is a priority to ensure that what we develop works with emerging and established standards,” said Mark Himelstein, CTO at RISC‑V International. “The joint working group will collaborate with various RISC‑V groups to review the OmniXtend protocol with a focus on cache management, paying close attention to coherency enablement for RISC‑V members.”

“The newly formed OmniXtend working group will set the standard for open, coherent heterogeneous compute architectures,” said Rob Mains, general manager at CHIPS Alliance. “We plan to allow a mixture of hardware IP blocks, giving developers greater design flexibility to choose what works best for their specific application needs. We encourage the RISC‑V community to get involved in this important initiative, which will open new design possibilities with OmniXtend.”

Fast‑Track Architecture Extension Process

Last month, RISC‑V International introduced a fast‑track process to streamline the standardization of small architecture‑extension proposals. The process targets straightforward extensions that benefit a significant portion of the RISC‑V community, address a clear issue, fit cleanly into the existing architecture, and are free of contention.

The Fast‑Track Architecture Extension Process defines the steps for developing and standardizing extensions that meet these criteria while maintaining quality control under the oversight of the relevant RISC‑V standing committee. After internal review, proposals enter a 45‑day public review period.

Himelstein noted, “The Fast‑Track system enables us to more quickly address the needs of the RISC‑V community as the diversity of RISC‑V solutions and applications continues to grow exponentially.”

The ZiHintPause extension, which lets engineers reduce energy consumption, is the first to be ratified under this new process. It improves the performance of spin‑wait loops and allows multithreaded cores to temporarily relinquish extension resources. The extension adds a single PAUSE instruction (encoded as a HINT) to the ISA. Himelstein added, “The ratification of ZiHintPause demonstrates how this simplified process significantly accelerates the review of important extensions, while still maintaining RISC‑V’s core tenant of openness with a public review period.”

Greg Favor, co‑founder and CTO of Ventana Micro Systems, said, “This is an important extension for the RISC‑V ISA, and we are happy to see that ZiHintPause was able to be ratified quickly and is now available for the whole RISC‑V community to use. Fast‑Track maintains the necessary checks and balances to ensure extensions are properly designed and adhere to RISC‑V’s architectural approach, while paving the way for RISC‑V International to rapidly expand its set of standardized extensions.”

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