RISC‑V Summit 2020: Key Sessions & Highlights

The third annual RISC‑V Summit will take place online from December 8–10, 2020. The agenda spans three days of talks covering architecture, hardware, software, tools, verification, security, and real‑world case studies from the global RISC‑V ecosystem.

Technology leaders and research groups will present product updates, projects, and implementations, highlighting how the RISC‑V instruction set architecture (ISA) drives the next generation of hardware, software, and intellectual property (IP).

The event features an online exhibition hall, networking opportunities, and a full roster of speakers—including executives from Andes Technology, Alibaba, the CHIPS Alliance, Google, IBM, NXP Semiconductors, OneSpin Solutions, Red Hat, Seagate, SiFive, Western Digital, and more.

As a media partner, embedded.com will host a fireside chat on December 9 with David Patterson, the pioneer who coined “RISC” in 1980 and co‑author of the foundational textbook “Computer Architecture: A Quantitative Approach.”

The complete agenda is available online; visit the summit website for details.

Day 1 – Tuesday, 8 December 2020

Building an Open Edge Machine‑Learning Ecosystem with RISC‑V, Zephyr, TensorFlow Lite Micro, and Renode

Keynote panel featuring Tim Ansell (Google), Kate Stewart (Zephyr Project), Brian Faith (QuickLogic), and Michael Gielda (Antmicro) discusses how RISC‑V, Zephyr RTOS, TensorFlow Lite Micro, and Renode converge to create a vendor‑neutral, traceable ML development environment for edge devices.

Leveraging the RISC‑V Ecosystem to Deliver a Commercial Chip in Under $10 M

Dean Halle, CEO of Intensivate, explains the journey to a 12 nm commercial cluster CPU produced in under $10 million, spotlighting the role of the Rocket‑Chip RTL, FireSim FPGA emulation, and the Chisel hardware language.

Day 2 – Wednesday, 9 December 2020

RISC‑V in 5G New Radio Small‑Cell Base Stations

Gajinder Panesar (Mentor, Siemens) and Peter Claydon (Picocom) present a heterogeneous SoC that powers 5G NG small‑cell base stations with RISC‑V clusters and dedicated DSPs, detailing real‑time monitoring and embedded analytics that ensure strict timing compliance.

Secure IoT Firmware for RISC‑V

Cesare Garlati (Hex Five Security) and Sandro Pinto (Universidade do Minho) introduce an open, free secure IoT stack for RISC‑V, covering FPGA SoC, multi‑zone TEE, safety‑critical RTOS, TCP/IP, TLS‑ECC cryptography, and MQTT for OTA updates.

Day 3 – Thursday, 10 December 2020

Embedded Software Reimagined: Thread Processors Using RISC‑V

Russell Klein (Mentor Graphics) and Colin Walls (Mentor, Siemens) demonstrate how assigning tasks to dedicated RISC‑V cores simplifies real‑time scheduling, with 14 nm ASIC PPA metrics illustrating power, performance, and area trade‑offs.

A Guide to the RISC‑V Cryptography Extension

Ben Marshall (University of Bristol) and Barry Spinney (Nvidia) walk through the cryptography extension, covering instruction sets, implementation costs, and software performance gains across core classes.

CORE‑V‑VERIF: An Industrial‑Grade Verification Platform for RISC‑V Cores

Presented by Sven Byer (OneSpin Solutions), Steve Richmond (Silicon Labs), and Mike Thompson (OpenHW Group), this session details CORE‑V‑VERIF’s role in verifying CV32E40P, CV32A6, and CV64A6 cores, and offers a quick‑start training for future projects.

Register now for the 2020 Virtual RISC‑V Summit (December 8–10) and join keynotes, technical presentations, tutorials, and more. Visit the summit website and register here.