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Binary, Gray, and One‑Hot Encoding: A Practical Guide for FPGA State Machines

This article provides a detailed comparison of binary, Gray, and one‑hot encodings when implementing finite state machines (FSMs) on FPGAs. Understanding how synthesis tools evaluate and potentially transform these encodings is essential for achieving optimal performance and power efficiency.

Finite state machines are ubiquitous in digital design. Synthesis tools routinely analyze your RTL to detect FSMs and may rewrite state encodings to meet timing, area, or power goals. Even if you manually assign state codes, the tool can substitute different values—sometimes with a different bit width—based on its optimization strategy.

For a refresher on building FSMs in Verilog, see my article Creating Finite State Machines in Verilog.

Encoding Options: Binary, Gray, and One‑Hot

The three most common FSM encodings are binary, Gray, and one‑hot. Each offers distinct trade‑offs.

Binary Encoding

Binary encoding assigns the fewest possible bits to represent all states. It is the most space‑efficient choice, but state transitions can involve multiple bit changes, which may increase dynamic power.

Binary, Gray, and One‑Hot Encoding: A Practical Guide for FPGA State Machines

An example of binary encoding. Image by Steve Arar

Gray Encoding

Gray code ensures only one bit changes between consecutive states. When the FSM follows a predictable sequence, Gray encoding can reduce switching activity and lower dynamic power.

Binary, Gray, and One‑Hot Encoding: A Practical Guide for FPGA State Machines

The Gray code wheel. Image from Marie Christiano

One‑Hot Encoding

One‑hot encoding represents each state with a dedicated flip‑flop bit. While it consumes more logic resources and introduces many invalid combinations, it eliminates the need for state decoding, simplifying combinational logic and often improving timing at high clock frequencies.

Binary, Gray, and One‑Hot Encoding: A Practical Guide for FPGA State Machines

An example of one‑hot encoding. Image by Steve Arar

For deeper insights into state encoding in VHDL, consult Encoding the States of a Finite State Machine in VHDL by Steve Arar.

Choosing the Right Encoding

Determining the optimal encoding is context‑dependent and involves balancing area, timing, and power. General guidelines include:

Because the trade‑offs are nuanced, I recommend allowing the synthesis tool to choose the encoding. Nonetheless, I conducted comparative experiments across three major development tools and three distinct state machines to illustrate how each encoding performs in practice. The results are discussed in my next article.


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