CEVA-BX: A Unified DSP/MCU Processor for Next‑Gen IoT, Automotive, and Industrial Applications

CEVA has unveiled the CEVA‑BX hybrid processor alongside its WhisPro speech‑recognition engine. The CEVA‑BX fuses digital‑signal processor (DSP) and microcontroller (MCU) capabilities into a single silicon solution, meeting the rising demand for both high‑throughput signal processing and versatile computing across IoT, consumer, automotive, and industrial domains.

Traditionally, designers had to juggle separate MCUs and DSPs to satisfy mixed workloads such as cellular IoT, sensor fusion, and neural‑network inference. This approach often led to complex system‑on‑chip (SoC) designs or compromises in either signal‑processing performance or control flexibility. CEVA‑BX addresses this gap by delivering a parallel‑processing architecture that marries the speed of DSPs with the programmability of MCUs.

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Figure 1. CEVA‑BX block diagram. (Source: CEVA)

The core architecture features an 11‑stage variable‑length pipeline and two scalar processing units (SPUs) with native support for complex math, FFT, and division acceleration. Optional double‑, single‑, and half‑precision floating‑point units enable a broad range of workloads. SIMD extensions provide the vector processing required for neural‑network inference and other data‑parallel tasks. To accommodate MCU‑style control, the instruction set offers full C‑language compatibility, a generous register file, and optimized branching/loop buffers that reduce code size and boost performance.

Memory is handled through a fully cached subsystem that supports up to 4 GB of program and data space, with dedicated master ports for each memory domain. Developers can further enhance application complexity by leveraging CEVA‑Connect’s automatic queue and buffer management, allowing integration of co‑processors and the creation of multi‑core CEVA‑BX clusters (Figure 2).

Figure 2. CEVA‑Connect data transfers. (Source: CEVA)

Initially available in two configurations, the CEVA‑BX1 offers a single 32×32‑bit MAC and four 16×16‑bit MACs, while the CEVA‑BX2 delivers four 32×32‑bit MACs and eight 16×16‑bit MACs. Both support 16×8‑bit and 8×8‑bit MAC operations. The CEVA‑BX2 is tailored for high‑intensity workloads such as 5G PHY control, multi‑microphone beamforming, and deep neural networks for speech recognition, delivering up to 16 GMACs per second. The CEVA‑BX1 targets low‑ to mid‑range DSP tasks—cellular IoT, protocol stacks, and always‑on sensor fusion—providing up to 8 GMACs per second. Security is ensured through dedicated trusted execution modes that meet stringent safety standards.

CEVA backs the hardware with a robust software ecosystem: an advanced LLVM compiler, an Eclipse‑based debugger, DSP and neural‑network libraries, support for Android NN API, ARM NN, and TensorFlow Lite, and a choice of leading real‑time operating systems. For more details, visit the CEVA‑BX product page.

WhisPro Speech Recognition

CEVA’s WhisPro technology accelerates the deployment of voice‑activated smart devices that connect to cloud‑based assistants such as Amazon Alexa, Google Assistant, and Baidu DuerOS. Designed for always‑on edge scenarios, WhisPro employs a scalable recurrent neural network (RNN) that can recognize a single trigger phrase or multiple phrases simultaneously, supporting multiple AI assistants. Built with noise immunity, WhisPro achieves over 95% speaker‑independent wake‑phrase accuracy while keeping power consumption and computational load low. For enhanced noise resilience, developers can pair WhisPro with CEVA’s ClearVox noise‑reduction front end. Together, they deliver a noise‑tolerant voice‑activation solution for CEVA‑TeakLite‑4, CEVA‑X2, and CEVA‑BX devices. For more information, visit the CEVA WhisPro product page.