Graphene‑Coated Porous Silicon Electrodes Deliver Exceptional Supercapacitor Performance

Abstract

We report a high‑performance electrochemical double‑layer supercapacitor (EDLC) electrode comprising few‑layer graphene‑passivated porous silicon (PSi). The PSi matrix was fabricated by electrochemical etching of a p‑type silicon wafer, followed by Ni‑assisted chemical vapor deposition (CVD) that simultaneously grows conformal graphene layers and restructures the pore network as the annealing temperature rises. The optimized hybrid porous PSi electrode exhibits an areal capacitance of 6.21 mF cm^–2 at an ultra‑high scan rate of 1000 mV s^–1 and an unprecedented cyclic stability of 131 % after 10 000 cycles. Introducing micropores via KOH activation on the graphene surface further increases the specific surface area, boosting the areal capacitance by 31.4 % to 8.16 mF cm^–2. These results demonstrate a robust, high‑rate energy storage platform suitable for microelectronic devices.

Background

Miniaturized electronics, including MEMS, micro‑sensors, and implantable biomedical devices, demand compact, reliable, and high‑power sources [1,2]. Lithium‑ion batteries, though energy‑dense, suffer from aging and instability, limiting their suitability for long‑term applications [3–6]. Electrochemical double‑layer capacitors (EDLCs) offer superior cycle life and high power density because charge storage occurs at the electrode–electrolyte interface rather than through sluggish bulk diffusion [7–10]. Enhancing the specific surface area (SSA) of electrode materials is therefore key to maximizing EDLC performance.

Silicon, abundant and inexpensive, has been extensively employed in electronics and photovoltaics. Porous silicon (PSi) can be produced by electrochemical etching, yielding a controllable porous network with high SSA [11–14]. However, PSi suffers from poor conductivity and chemical instability due to surface traps and high reactivity [15–16]. A common strategy to mitigate these issues is to coat PSi with conductive, chemically robust materials such as graphene, which offers exceptional electronic conductivity, mechanical strength, and chemical stability [17–18]. Traditional transfer methods cannot uniformly coat high‑aspect‑ratio nanostructures; thus, in‑situ growth via Ni‑assisted CVD is preferable for conformal coverage.

While EDLCs currently lag behind batteries in energy density by one to two orders of magnitude, optimizing pore size distribution and surface chemistry can raise SSA to 3100 m² g^–1 through graphene activation (KOH + C → K + H₂ + K₂CO₃) [20–21]. In this work, we present a systematic study of graphene‑coated PSi electrodes fabricated via Ni‑assisted CVD, exploring the influence of annealing temperature on pore restructuring, graphene quality, and electrochemical performance.

Methods / Experimental

Electrochemical Etching of Porous Silicon

A p⁺ silicon wafer was anodized against a titanium plate (anode) in a 1:1 volume mixture of hydrofluoric acid and dehydrated alcohol at a current density of 1 mA cm^–2 for 10 min, forming a ~15 µm thick porous layer. The wafer was then diced into 2 × 1 cm² pieces for subsequent processing.

Ni‑Assisted CVD of Graphene

Ni ingots (99.99 % purity) and the etched PSi were placed in opposite ends of a quartz tube. Methane (≈ 50 sccm) was introduced as the carbon source, and a reducing forming gas (Ar/H₂, 100/20 sccm) prevented Ni oxidation. The system was heated to 1000–1100 °C under 60 Torr pressure, allowing graphene to grow directly on the PSi surface while the porous structure reorganizes.

Characterization

Field‑emission SEM (JSM‑6500F, 15 kV) and TEM (JEM‑3000F, 300 kV) examined morphology and microstructure. Raman spectroscopy (Horiba LabRam HR800, 632.8 nm) assessed graphene quality and uniformity.

Results and Discussion

Figure 1 illustrates the full fabrication sequence: electrochemical etching, Ni‑assisted CVD, and pore reorganization. SEM images (Fig. 2) reveal that annealing at 1000 °C preserves the mesoporous network (~11 nm pores), while higher temperatures (1050–1100 °C) fuse pores into hybrid and macroporous structures (> 50 nm). Correspondingly, electrical resistance drops from 3.3 × 10⁷ Ω (as‑etched) to 22 Ω (1100 °C) due to the conductive graphene layer.

Raman spectra (Fig. 3) show clear G, D, and 2D bands, confirming few‑layer graphene. The D band intensity decreases with temperature, indicating defect healing, and the I_2D/I_G ratio peaks at 1050 °C, marking the optimal annealing condition for crystalline graphene on PSi.

Cross‑sectional Raman mapping confirms uniform graphene coverage across the entire PSi matrix. TEM images reveal ~10 graphene layers enveloping the porous silicon framework.

Electrochemical testing in 0.5 M Na₂SO₄ (neutral electrolyte) shows that graphene passivation enhances capacitance by 2–3 orders of magnitude. The hybrid porous PSi electrode achieves 6.21 mF cm^–2 at 1000 mV s^–1, while the mesoporous variant attains 8.48 mF cm^–2 at 5 mV s^–1 but drops sharply at high scan rates. The macroporous sample retains 87.5 % capacitance at 1000 mV s^–1 due to rapid ion transport.

Charge‑discharge curves (Fig. 6) display triangular profiles with >90 % coulombic efficiency. Over 10 000 cycles at 100 mV s^–1, the hybrid electrode’s capacitance increases by 31 %, attributed to improved electrolyte wettability from surface oxidation.

Introducing micropores (< 5 nm) via KOH activation further elevates SSA. After a 1‑min KOH treatment followed by 30 min vacuum annealing at 800 °C, the areal capacitance rises to 8.16 mF cm^–2 at 5 mV s^–1 (31.4 % increase). At higher scan rates (> 200 mV s^–1), capacitance slightly declines due to increased mass‑transfer resistance in the ultramicropores.

Table 1 (not shown) compares these results with other Si‑based supercapacitors, highlighting the superior cycling stability of the activated hybrid PSi electrode.

Conclusions

We have fabricated graphene‑coated porous silicon electrodes with controllable pore structures via Ni‑assisted CVD. The hybrid porous design, further activated by KOH, delivers an areal capacitance of 8.16 mF cm^–2 at 1000 mV s^–1, a 131 % increase after 10 000 cycles, and excellent rate capability. These findings establish activated hybrid porous PSi as a promising, high‑rate, long‑life energy storage platform for microelectronic applications.