Ultra‑Low Specific On‑Resistance LDMOS with Enhanced Dual‑Gate and Partial P‑Buried Layer

Background

Modern analog power ICs demand transistors with both low on‑resistance and high breakdown voltage. For LDMOS devices, the drift region traditionally dominates the resistance–voltage trade‑off [1–20]. In our previous work, an ultra‑shallow trench isolation (USTI) LDMOS was introduced [21], optimizing depth and corner angle for superior performance. However, in low‑voltage regimes the channel resistance becomes a significant contributor to R_on,sp, necessitating new design strategies that target both drift and channel regions.

Method

We developed an LDMOS featuring an enhanced dual‑gate and a partial P‑buried layer. Device physics were modeled using the IMPACT.I, BGN, CONMOB, FLDMOB, SRH, and SRFMOB simulation packages. An analytical on‑resistance framework was derived to dissect the contributions of the drift and channel resistances, guiding the systematic optimization of the N‑buried and partial P‑buried layers for minimal R_on,sp and maximal BV.

Results and Discussion

Figure 1a illustrates the cross‑section of the proposed device, highlighting the dual‑gate structure (trench gate + N‑buried layer) and the partial P‑buried layer under the drift region. The N‑buried layer supplies a low‑resistance path beneath the P‑well, substantially reducing R_c, while the partial P‑buried layer extends the depletion region and suppresses peak electric fields, thereby enhancing BV. The key dimensional parameters are summarized in Table 1.

a Schematic cross‑section view of the ultra‑low specific on‑resistance LDMOS with enhanced dual‑gate and partial P‑buried layer. b Equivalent on‑resistance model for the proposed device.

Figure 1b depicts the equivalent on‑resistance model, where the total on‑resistance is the series sum of the drift resistance (R_d) and the channel resistance (R_c). In the channel, the surface‑gate and trench‑gate paths are parallel, yielding R_c = (R_chs + R_acc)‖(R_cht + R_nb). Reducing R_nb via a highly doped N‑buried layer directly lowers R_c without affecting other performance metrics. The drift resistance was minimized by incorporating the partial P‑buried layer, leveraging the RESURF effect as demonstrated in our earlier study.

Figure 2 shows the dependence of R_c on the N‑buried layer doping concentration (N_nb) for single‑gate and dual‑gate configurations. The dual‑gate structure yields a 34 % reduction in R_c at N_nb = 5.5 × 10¹⁶ cm⁻³. Further doping increases R_c continuously until punch‑through occurs at ≈1.05 × 10¹⁷ cm⁻³. The analytical model aligns closely with simulation, validating its use for design optimization.

Numerical and analytical R_c as a function of N_nb with single‑gate and dual‑gate (Z = 1 cm). N_d denotes the N‑drift doping concentration.

Figure 3a explores the impact of N_nb on BV for various P‑well doping levels (N_pwell). BV remains stable at low N_nb but decreases when punch‑through initiates. A P‑well doping of 2 × 10¹⁷ cm⁻³ is selected to balance threshold voltage and breakdown performance. Figure 3b visualizes the current density profile at breakdown, confirming the absence of punch‑through for the chosen parameters.

a Numerical BV versus N_nb for different N_pwell. b Current density profile at breakdown for N_nb = 10.5 × 10¹⁶ cm⁻³ and 14.5 × 10¹⁶ cm⁻³ with N_pwell = 2 × 10¹⁷ cm⁻³.

To further reduce drift resistance while preserving high BV, a partial P‑buried layer (ΔL_pb) is introduced beneath the N‑drift region. Figure 4a demonstrates that a ΔL_pb of 0.1 µm and a doping of 1 × 10¹⁷ cm⁻³ yield the peak BV of 43 V. The equipotential contour in the partial P‑buried configuration extends deeper into the substrate, reducing peak electric fields at the N‑drift/P‑buried interface (Figure 4b). This design shift alleviates vertical field stress and promotes charge balance.

a BV versus ΔL_pb for different N_pb; inset shows the equipotential contour for N_pb = 1 × 10¹⁷ cm⁻³. b Electric field distribution at the surface and the P-buried/N-drift junction interface.

Charge‑balance analysis (Figure 5a) indicates that optimal N_pb of 1 × 10¹⁷ cm⁻³ paired with an N‑drift doping of 5.5 × 10¹⁶ cm⁻³ achieves the target BV > 40 V while keeping R_on,sp low. Figure 5b highlights the influence of the STI thickness (T_sti); a thickness of 0.3 µm yields a BV of 43 V and mitigates field peaks under the poly field‑plate edge.

a Numerical (dotted) and analytical (solid) BV and R_on,sp versus N_pb for various N_d. b Numerical (dotted) and analytical (solid) BV and R_on,sp versus T_sti.

Figure 6 benchmarks the proposed LDMOS against existing Bipolar‑CMOS‑DMOS (BCD) technologies. The design leverages the same mask set for the N‑buried and P‑well layers, ensuring compatibility with our proven BCD process flow. Compared to our earlier LDMOS (8.5 mΩ·mm² vs 13.3 mΩ·mm²), the new structure achieves a 37 % reduction in specific on‑resistance while delivering 43 V BV.

The benchmark of existing BCD technologies and the proposed LDMOS.

Conclusion

We have introduced an LDMOS transistor that simultaneously reduces the channel resistance via a highly doped N‑buried layer and elevates breakdown voltage through a partial P‑buried layer. The resulting device attains 8.5 mΩ·mm² specific on‑resistance at 43 V BV, representing a 37 % improvement over prior work. The fabrication flow is fully compatible with existing BCD processes, enabling immediate integration into advanced analog power ICs. As semiconductor dimensions continue to shrink, further reductions in R_on,sp can be achieved by shortening the channel length while maintaining the demonstrated architectural benefits.

Abbreviations

BCD

Bipolar‑CMOS‑DMOS

BV

Breakdown voltage

LDMOS

Lateral double‑diffused metal‑oxide‑semiconductor transistor

RESURF

Reduce surface‑field

R_on,sp

Specific on‑resistance

USTI

Ultra‑shallow trench isolation