Enhanced Baliga’s Figure‑of‑Merits in a Novel GaN Nano‑Pillar Vertical FET with 2DEG Channel and Patterned Substrate

Abstract

A new enhancement‑mode vertical GaN field‑effect transistor (FET) incorporating a two‑dimensional electron gas (2DEG) channel and a substrate pattern (SP) is presented. By tailoring the SP width and height, the device achieves a lower on‑state resistance (R_ON) while maintaining a high breakdown voltage (BV). Experimental‑calibrated ATLAS simulations demonstrate that a 700‑nm‑long and 4.6‑µm‑wide SP yields a six‑fold increase in Baliga’s Figure‑of‑Merits (BFOM = BV²/R_ON) compared to an unpatterned counterpart, without sacrificing device area. The nanoscopic footprint of the pillar and SP permits high‑density integration, positioning this architecture as a strong candidate for future power electronics.

Background

Wide‑bandgap semiconductors such as ZnO, In₂O₃, SiC, and GaN have attracted significant attention due to their high breakdown voltages and superior thermal stability. In particular, the lateral AlGaN/GaN high‑electron‑mobility transistor (HEMT) is a leading candidate for replacing Si devices in power and RF applications. Numerous strategies—including p‑type caps, fluorine ion implantation, thin barriers, double‑channel designs, and field‑coupled gates—have been explored to realize enhancement‑mode HEMTs that simplify driver circuits. However, these approaches face challenges such as threshold voltage non‑uniformity, limited BFOM, and excessive chip area usage. The trade‑off between drift length and BV further hampers device scaling.

Vertical GaN FETs (VFETs) mitigate many of these issues by exploiting the full vertical channel and offering easier enhancement‑mode operation. Recent studies have focused on boosting BV while reducing R_ON through various structural innovations, yet the absence of a high‑mobility 2DEG often results in higher resistances, limiting BFOM optimization.

Our work introduces a vertical GaN FET that simultaneously incorporates a 2DEG channel and a patterned substrate. This combination balances low R_ON with high BV, while the nanoscale pillar and SP allow for dense device integration.

Method

The device is fabricated on a standard Al_0.23GaN/GaN wafer, with a heavily doped n‑type substrate serving as the drain. Layer thicknesses are: SiN (105 nm), AlGaN (20 nm), and GaN (5 µm). A 2×10¹⁶ cm⁻³ n‑GaN buffer and a 2×10¹⁷ cm⁻³ p‑GaN cap form the buffer and composite channel, respectively. A thin AlGaN layer induces the 2DEG, and the SP—typically Al₂O₃—is grown on the substrate.

Enhanced Baliga’s Figure‑of‑Merits in a Novel GaN Nano‑Pillar Vertical FET with 2DEG Channel and Patterned Substrate

The fabrication sequence is straightforward: (1) epitaxial growth of the conduction substrate and SP layer; (2) selective SP pattern etching; (3) deposition and polishing of the n‑GaN buffer; (4) AlGaN barrier and p‑GaN cap deposition; (5) electrode formation and passivation.

ATLAS simulations are calibrated against experimental data from an enhancement‑mode HEMT with a p‑GaN cap. Device parameters are listed in Table 1, and interface trap characteristics at the SP/GaN boundary are derived from capacitance measurements. Polarization charges are calculated via a quadratic fitting approach.

Physics Mechanism

In the on‑state, the SP‑VFET exhibits a highly conductive path due to the 2DEG, while the narrow vertical channel limits overall conductance. The 2DEG at the AlGaN/GaN interface sustains lateral current flow, partially compensating for the vertical resistance. Devices lacking the 2DEG channel experience markedly higher resistance.

Simulations show that the p‑GaN cap length has minimal impact on the peak electric field until it exceeds 700 nm, at which point the cap covers the entire surface. The field peak remains at the p‑GaN corner regardless of length, but a longer cap flattens the field distribution, slightly increasing resistance due to 2DEG depletion.

An analytical on‑state resistance model (Fig. 4) shows that the 2DEG channel dominates conductance; the vertical path resistance becomes significant only when the SP length grows. The on‑state resistance increases hyperbolically with SP length but remains largely unaffected by SP height below 4.7 µm, confirming the 2DEG’s resilience.

In the off‑state, the SP’s negatively charged interface traps redistribute the electric field under the p‑GaN cap, reducing peak fields and expanding the depletion region. This redistribution improves breakdown voltage while only modestly increasing R_ON due to 2DEG compensation. Consequently, BFOM fluctuates with SP dimensions.

Result and Discussion

Transfer and output characteristics for devices without SP (Fig. 7) show negligible dependence on p‑GaN cap length, confirming the 2DEG’s role in maintaining consistent conductance. The minimum cap length is 400 nm to avoid excessive field crowding near the gate.

For SP‑VFETs (Fig. 8), the on‑state resistance remains constant for SP heights below 4.7 µm but increases with SP length, consistent with the narrowed vertical channel. The 2DEG channel remains largely unaffected by moderate SP heights; only when the SP is adjacent to the 2DEG does the negative charge significantly deplete it.

Current density maps (Fig. 9) confirm that the SP narrows the vertical channel, while lateral current remains primarily carried by the 2DEG. The overall current density changes only slightly with SP height.

Extracted R_ON and BV (Fig. 10a) reveal a hyperbolic increase of resistance with SP length, while BV rises until the SP length reaches 700 nm. The BFOM peaks at 125 MW cm⁻² for a 700 nm SP length and 4.6 µm height, representing a six‑fold improvement over the unpatterned device.

Enhanced BV arises from the SP’s ability to redistribute electric field, mitigating peak concentrations under the p‑GaN cap. The negatively charged interface traps create an additional field that counteracts the depletion‑induced field, thereby expanding the depletion region and reducing leakage paths. Simulated electric field maps (Fig. 12) and cut‑line analyses (Fig. 13) illustrate how increasing SP length flattens the field and concentrates it across the SP edge, which possesses a higher critical field.

Conclusion

This study demonstrates a novel GaN vertical FET that leverages a 2DEG channel and a nanoscale substrate pattern to markedly improve BFOM. By mitigating the electric‑field peak under the p‑GaN cap and creating a new high‑field region across the SP, the device achieves a six‑fold BFOM enhancement at a 700 nm SP length and 4.6 µm height. The compact pillar design and minimal SP footprint make the architecture highly suitable for dense power‑integrated applications.

Abbreviations

n_A: Doping concentration of p‑type GaN
n_D: Doping concentration of n‑type GaN
2DEG: Two‑dimensional electron gas
Al_0.23GaN: Aluminum gallium nitride (23 % Al)
Al₂O₃: Aluminum oxide
BFOM: Baliga’s Figure‑of‑Merits
SP: Substrate pattern
E‑field: Electric field
FET: Field‑effect transistor
GaN: Gallium nitride
HEMT: High‑electron‑mobility transistor
H_G: Gate height
H_W: Substrate pattern height
L_D: Device length
L_G: Gate length
L_P: p‑GaN cap length
L_W: Substrate pattern length
SiN: Silicon nitride
SP‑VFET: Vertical field‑effect transistor with substrate pattern
W_D: Device depth
σ_p: Polarization charge

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