Silicon Labs Launches PCI Express Gen 5 Timing Solutions with Unmatched Jitter Performance and Power Efficiency

Silicon Labs has unveiled a comprehensive line of timing devices that deliver industry‑leading jitter performance while exceeding the stringent requirements of the PCI Express 5.0 specification. The Si5332 “any‑frequency” clock family produces reference clocks with an RMS jitter of just 140 fs, enabling PCIe SerDes to operate at peak speeds with ample design margin.

These clocks can generate any combination of PCIe and general‑purpose frequencies, making it possible to consolidate clock trees across a wide range of platforms—from networking cards to high‑performance computing accelerators.

For data‑center and edge applications that run on low‑power 1.5 V or 1.8 V rails, Silicon Labs also offers the Si522xx PCIe clock generators and the Si532xx PCIe buffer families. Each device supports two, four, eight, or twelve PCIe Gen 1/2/3/4/5‑compliant outputs, making them ideal for clocking diverse PCIe endpoints.

These solutions are the industry’s lowest‑power PCIe clocks and buffers, thanks to Silicon Labs’ proven push‑pull high‑speed current steering logic (HCSL). HCSL eliminates the need for external termination resistors, a requirement of conventional constant‑current drivers, further reducing board complexity and power draw.

Fully compliant with PCIe Gen 5 Common Clock, Separate Reference No Spread (SRNS), and Separate Reference Independent Spread (SRIS) architectures, the new products simplify PCB layout by obviating discrete power‑supply filtering components. Designers can drop‑in the Si5332, Si522xx, or Si532xx into existing Gen 1/2/3/4 designs to upgrade to Gen 5 without redesigning the clock tree.

To support these advances, Silicon Labs has updated its PCI Express clock jitter tool. The software now includes the precise filters required for Gen 5 reference clock measurements, ensuring that users apply the correct settings per the PCI‑SIG specifications and receive results in an intuitive format.