Lattice & Etron Unveil Compact, Low‑Power Memory Controller for Edge AI Workloads

Lattice Semiconductor Corp. and Etron Technology Inc. have introduced a memory controller reference design tailored for Etron’s low‑pin‑count RPC DRAM. The design couples Etron’s compact DRAM with Lattice’s low‑power ECP5 FPGA, which handles the AI and smart‑vision processing directly on the edge. Target applications span industrial cameras, drones, AR/VR systems and advanced driver‑assist (ADAS) platforms.

The reference design tackles the dual challenges of high data volume and stringent latency/privacy requirements that push many edge devices to offload processing to the cloud. By moving analysis to the device, OEMs can keep power budgets tight while preserving user data integrity.

Compared to a traditional DDR3‑based system, the new solution delivers 15 % lower power consumption and occupies a footprint smaller than the 9 × 13 mm BGA package used by standard DDR3 chips. Moreover, Lattice’s sensAI software stack and design tools eliminate the need for deep FPGA expertise, streamlining integration.

Alongside the reference design, Lattice launched sensAI 3.0—a next‑generation on‑device AI stack that doubles performance and cuts power usage in half. It supports CrossLink‑NX FPGAs and offers custom CNN IP and an accelerator IP that simplifies deployment of common neural networks while fully exploiting FPGA parallelism.

The package includes user‑friendly tools such as a GUI‑based memory code generator and a Verilog simulation model. Etron plans to release application demos that combine the sensAI stack with the RPC DRAM controller in Q3 2020.

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