Optimizing a-IGZO TFTs for Large‑Area Displays with a Clean Etch‑Stopper Nano‑Layer Process

Background

The demand for higher‑resolution, larger‑panel flat‑panel displays drives the search for semiconductor backplanes with superior electron mobility. Metal‑oxide semiconductors, particularly a‑IGZO, offer mobilities of 5–10 cm²/V s and off‑currents below 10 pA, making them attractive alternatives to silicon TFTs [1–4]. However, a‑IGZO’s weak chemical resistance to standard etchants used in five‑mask BCE processes hampers its adoption. Al‑based etchants dissolve a‑IGZO within seconds [11–13], and even the milder H₂O₂‑based Cu wiring etchants still damage the channel, leading to stoichiometric imbalance, reduced uniformity, and compromised device reliability [14–18]. Existing six‑mask etch‑stopper (ES) solutions mitigate contamination but increase mask count, parasitic capacitance, and reduce open‑area ratios [16–18]. Recent five‑mask half‑tone and lift‑off techniques remain inaccessible for a‑IGZO due to exposure of the active layer to stripping and photoresist chemicals, further degrading yield [19–21]. Therefore, a cost‑effective, mask‑efficient process that preserves the a‑IGZO interface is essential for industrial scalability.

The CL‑ES approach satisfies these requirements by integrating an ESL into the standard five‑mask BCE workflow. The ESL is deposited after the a‑IGZO layer and before S/D patterning, forming a protective nano‑mask that shields the channel from etchants, photoresists, and solvents. This strategy not only protects the a‑IGZO interface but also enables simultaneous etching of the a‑IGZO film and S/D metallization, reducing overlay errors and parasitic capacitance. The result is a backplane that retains the throughput of BCE while delivering the cleanliness and performance benefits of an etch‑stopper design.

Methods/Experimental

Fabrication of a-IGZO‑Based TFT Backplane

The CL‑ES process is illustrated in Fig. 1. A double‑layer Mo/Cu (30 nm/250 nm) gate electrode is first deposited to ensure low resistivity. The gate insulator stack—Si₃N₄ (300 nm) followed by SiO₂ (100 nm)—is grown by plasma‑enhanced CVD (PECVD) to block Cu oxidation and prevent ion diffusion. A 30 nm a‑IGZO film (In₂O₃:Ga₂O₃:ZnO = 1:1:1) is sputtered at room temperature and annealed at 330 °C in dry air for 1 h to achieve the target mobility range [6–10]. An SiO₂ etch‑stopper layer (~100 nm) is then deposited by PECVD under identical power and pressure conditions, ensuring an intimate interface with the a‑IGZO film. Dry etching (CF₄/O₂, 2000/800 sccm) patterns the ESL, exposing only the desired channel region. Because the a‑IGZO is bombarded by CF₄ plasma during ESL patterning, it becomes conductive, forming an intrinsic ohmic contact with the subsequent Mo/Cu/Mo S/D stack (30 nm/300 nm/30 nm) sputtered under the same conditions. A selective H₂O₂–fluoride etchant removes excess metal without damaging the ESL or a‑IGZO. The passivation stack consists of a 250 nm SiO₂ layer followed by a 200 nm Si₃N₄ layer, both deposited by PECVD. Finally, a 40 nm indium tin oxide (ITO) pixel electrode is sputtered, and the device is annealed at 230 °C for 1 h in dry air. The entire process uses five masks, identical to the conventional BCE workflow, ensuring compatibility with existing AM‑LCD fabs. For comparison, a BCE‑structured a‑IGZO TFT backplane was fabricated following the standard five‑mask BCE recipe, with a 70 nm a‑IGZO channel to compensate for etch loss.

Characterization

Electrical measurements were performed at room temperature with a Keysight 4082A parametric tester. Negative bias temperature illumination stress (NBTIS) was applied at V_GS = –30 V, V_DS = 15 V, 60 °C, and 5000 cd/m² illumination for 3600 s [23]. Positive bias temperature stress (PBTS) used V_GS = 30 V, V_DS = 15 V, 60 °C for the same duration [24]. All measurements were taken across 42 random points on the 8.5‑generation substrate to assess uniformity.

Results and Discussion

Figure 2 highlights the CL‑ES fabrication flow, where the ESL nano‑mask protects the a‑IGZO channel from etchant exposure while enabling simultaneous S/D etching, thereby reducing overlay steps and parasitic capacitance. SEM images (Fig. 3) confirm the presence of the ESL between the a‑IGZO film and the S/D electrodes in CL‑ES devices, whereas BCE devices show the a‑IGZO channel directly beneath the passivation layer.

Electrical performance comparisons (Fig. 4) show that CL‑ES TFTs achieve a V_th of –0.8 V, SS of 0.18 V/dec, and a mobility of 8.05 cm²/V s, outperforming BCE TFTs (V_th = +0.5 V, SS = 0.77 V/dec, mobility = 6.03 cm²/V s). The CL‑ES channel length (~10 µm) is effectively determined by the ESL pattern rather than the electrode spacing, explaining the slightly lower on‑current compared to the 5 µm BCE channel.

Uniformity metrics across 42 measurement points (Fig. 5) reveal a V_th spread of 0.72 V for CL‑ES versus 2.14 V for BCE, underscoring the ESL’s role in mitigating chemical contamination and carrier‑trap density at the a‑IGZO/insulator interface.

Reliability tests further demonstrate the CL‑ES advantage. Under NBTIS, V_th shifts of –0.51 V (CL‑ES) and –3.88 V (BCE) are observed, with negligible SS variation (<0.1 V/dec) for CL‑ES. PBTS results show V_th shifts of +1.94 V (CL‑ES) and +5.58 V (BCE), and residual on‑current ratios of 88.2 % versus 41.3 %, respectively. These findings confirm that the ESL preserves interface integrity and reduces trap formation under stress conditions.

Overall, the CL‑ES process delivers superior uniformity, mobility, and stress tolerance while maintaining the mask count and device area of BCE. This combination of performance and manufacturability positions CL‑ES as a practical solution for next‑generation large‑area LCD backplanes.

Conclusions

The Clean Etch‑Stopper (CL‑ES) process successfully integrates a 100 nm SiO₂ ESL into a five‑mask a‑IGZO TFT workflow, preserving the throughput of BCE while eliminating chemical exposure of the channel. The resulting backplanes exhibit a V_th distribution of 0.72 V, a mobility of 8.05 cm²/V s, and SS of 0.18 V/dec across a 2200 mm × 2500 mm substrate. Reliability testing shows V_th shifts of –0.51 V (NBTIS) and +1.94 V (PBTS) after 3600 s, with minimal SS drift, confirming enhanced stability. By overcoming the chemical‑resistance bottleneck, the CL‑ES technique paves the way for economically viable, high‑resolution, large‑panel LCD production.

Abbreviations

a-IGZO:

Amorphous indium‑gallium‑zinc‑oxide

AM‑LCD:

Active‑matrix liquid crystal display

BCE:

Back‑channel etch

ESL:

Etch‑stopper layer

GOA:

Gate drive on array

NBTIS:

Negative bias temperature illumination stress

PBTS:

Positive bias temperature stress

SiNx:

Silicon nitride

SiOx:

Silicon oxide

SS:

Subthreshold swing

TFT:

Thin film transistor

TN LCD:

Twisted nematic liquid crystal display