Tunable P‑ to N‑Type Behavior in Multi‑Layer MoTe₂ Transistors and Their Application in Complementary Inverters

Background

Two‑dimensional (2D) materials, such as graphene, can be exfoliated into atomically thin layers, opening new avenues for exploring 2D physics and device applications [1–9]. Transition‑metal dichalcogenides (TMDs) possess sizable band gaps and exhibit mechanical flexibility and chemical inertness, making them attractive for next‑generation field‑effect transistors (FETs), inverters, light‑emitting diodes, and van der Waals heterostructures [2–28].

2H‑molybdenum ditelluride (2H‑MoTe₂) is a prototypical TMD, with an indirect band gap of 0.83 eV in bulk and a direct gap of 1.1 eV in the monolayer limit [29–30]. It has been investigated for spin‑tronics, FETs, photodetectors, and solar cells [31–39]. Because multi‑layer 2H‑MoTe₂ exhibits a large surface‑to‑volume ratio, its electronic properties are highly susceptible to ambient adsorbates, which complicates the extraction of intrinsic transport characteristics.

In this study, we fabricate a multi‑layer 2H‑MoTe₂ transistor with source and drain electrodes, transferring a clean MoTe₂ flake to bridge the contacts. The entire device is exposed to air, allowing us to probe the effect of ambient species on charge transport. Vacuum‑ and temperature‑dependent measurements demonstrate that the transistor is intrinsically n‑type, while exposure to air induces p‑type doping. Density functional theory (DFT) calculations attribute the n‑type behavior to tellurium vacancies. By converting between p‑ and n‑type operation, we assemble a complementary inverter that exhibits symmetric input/output characteristics and a maximum gain of 9 at V_DD = 5 V.

Results and Discussion

Unlike previous reports, our device layout (Fig. 1a) begins with a back‑gated structure. We first pattern Cr/Au source–drain electrodes on a SiO₂/Si⁺ substrate. A multi‑layer MoTe₂ flake, prepared on a separate SiO₂/Si⁺ wafer by mechanical exfoliation, is then transferred to bridge the electrodes, ensuring a clean, polymer‑free channel (Fig. 1b). Because the entire flake is exposed to air, we can systematically study the influence of adsorbates on the intrinsic conductance.

AFM imaging confirms a 17 nm (≈24 monolayers) thickness (Fig. 1c,d), while Raman spectroscopy shows the characteristic A₁g (172 cm⁻¹), E¹₂g (233 cm⁻¹), and B¹₂g (289 cm⁻¹) modes, indicating high crystalline quality (Fig. 1e).

Back‑gated measurements were performed in a Lakeshore probe station coupled to an Agilent B1500A analyzer, with pressures down to 10⁻⁵ mbar and temperatures ranging from 9 K to 350 K. In ambient air at room temperature, the transfer curve (V_sd = 1 V, Fig. 2a) shows a p‑type response: the device turns on under negative gate bias and off under positive bias, with an on/off ratio of 6 × 10³, a subthreshold swing of 350 mV dec⁻¹, and a field‑effect mobility of 8 cm² V⁻¹ s⁻¹. Similar p‑type behavior is observed in devices of various thicknesses (5–85 nm) (Additional files S1–S3).

Figure 2b displays the output characteristics, revealing near‑linear I–V curves that imply a negligible Schottky barrier between Au and MoTe₂ in air. The on‑current scales linearly with V_sd (Fig. 2c), while the off‑current rises with V_sd, reducing the on/off ratio – a hallmark of trap states introduced by adsorbates. Hysteresis in the transfer curves further confirms the presence of such traps (Additional file S4).

To isolate the role of ambient species, we measured the device under progressively higher vacuum. As shown in Fig. 3a, increasing vacuum reduces the on‑current (due to higher resistance from the removal of adsorbates) and raises the off‑current, indicating that electron transport is progressively suppressed. The output curves at 2.9 × 10⁻⁵ mbar (Fig. 3b) exhibit a slightly larger Schottky barrier, supporting the conclusion that adsorbates modulate the effective barrier height.

Temperature‑dependent measurements (Fig. 4a) reveal that the transistor remains p‑type down to 20 K. Both on‑ and off‑currents decrease with temperature, while the on/off ratio improves. Arrhenius plots (Fig. 4c) show a thermally activated regime above 100 K and a tunneling‑dominated regime below, allowing extraction of an effective Schottky barrier height below 120 meV (Fig. 4d). Despite the reduction of adsorbates at low temperatures, the residual species still influence the conductance.

We further annealed the device to 350 K in vacuum (Fig. 5a). The transfer curve shifts from p‑ to n‑type: at 350 K the device is off under negative gate bias and on under positive bias, with an on/off ratio of 3.8 × 10², a subthreshold swing of 1.1 V dec⁻¹, and a mobility of 2 cm² V⁻¹ s⁻¹. After holding the device in vacuum for 12 h at room temperature, the n‑type behavior persists (Fig. 6a). Additional annealing at 523 K in Ar further confirms the stability of the n‑type state (Additional files S5).

DFT calculations for a 4 × 4 monolayer supercell reveal that a tellurium vacancy introduces a defect state just below the conduction band, explaining the intrinsic n‑type conductance (Fig. 7). Conversely, exposure to ambient O₂/H₂O leads to charge transfer from MoTe₂ to the oxygen/water redox couple (Fig. 8), resulting in p‑type doping. The work function of MoTe₂ (4.1 eV) is lower than that of the redox couple (> 4.83 eV), driving electron transfer and hole creation in the material.

Finally, we assembled a complementary inverter using the p‑ and n‑type transistors (Fig. 9a). With a V_DD of 5 V in 8 × 10⁻⁵ mbar vacuum, the inverter shows a symmetric voltage transfer characteristic centered at V_DD/2 (Fig. 9d) and noise margins of 1.54 V (low) and 1.77 V (high). The voltage gain rises with V_DD, reaching 9 at 5 V (Fig. 9f). These results demonstrate that MoTe₂ can serve as the active channel in high‑performance complementary logic devices.

Conclusions

In summary, we fabricated air‑stable p‑type multi‑layer MoTe₂ transistors and demonstrated that their intrinsic n‑type behavior can be uncovered by vacuum annealing. The n‑type conductance originates from tellurium vacancies, as confirmed by DFT. Ambient oxygen and water act as acceptors via the redox couple, converting the device to p‑type. Both device types exhibit reduced Schottky barriers in the presence of adsorbates, facilitating high performance. Leveraging these dual‑type transistors, we constructed a complementary inverter with a voltage gain of nine, illustrating the viability of MoTe₂ for future low‑power, flexible electronics.

Methods/Experimental

Device fabrication followed a standard back‑gated geometry. First, Cr/Au (5 nm/100 nm) source, drain, and gate electrodes were patterned on a 300‑nm SiO₂/p⁺‑Si wafer by UV photolithography, followed by selective SiO₂ etch. Multi‑layer MoTe₂ flakes were mechanically exfoliated from bulk crystals grown by chemical vapor transport (TeCl₄, 750–700 °C, 3 days) onto a separate SiO₂/Si⁺ substrate. The flakes were then transferred onto the patterned electrodes using a PVA transfer medium, dissolved in water and rinsed with isopropyl alcohol. The devices were annealed in a chemical vapor deposition chamber with a dry pump. Thicknesses were verified by AFM (SPA‑300HV) and Raman spectra were acquired with a LabRAM HR spectrometer (514 nm laser, 2.2 mW). Electrical characterization employed an Agilent B1500A analyzer with a Lakeshore probe station. DFT calculations were performed in VASP using PAW pseudopotentials, a 400 eV plane‑wave cutoff, 12 × 12 × 1 k‑point sampling for relaxation and 24 × 24 × 1 for electronic structure, within the GGA‑PBE framework.

Abbreviations

2D:

Two-dimensional

2H-MoTe₂:

2H-type molybdenum ditelluride

AFM:

Atomic force microscopy

DFT:

Density functional theory

DOS:

Density of states

FET:

Field‑effect transistor

GGA:

Generalized gradient approximation

IPA:

Isopropyl alcohol

Isd:

Source‑drain current

LED:

Light‑emitting diode

NM_H:

High‑level noise margin

NM_L:

Low‑level noise margin

PAW:

Projector‑augmented wave

PBE:

Perew‑Burke‑Ernzerhof

PVA:

Polyvinyl alcohol

SD:

Source‑drain

SS:

Subthreshold swing

TMDs:

Transition metal dichalcogenides

VASP:

Vienna ab initio simulation package

Vbg:

Back‑gate voltage

Vsd:

Source‑drain voltage

VTC:

Voltage transfer characteristics

ΦSB:

Schottky barrier height