Mastering SPICE: Common Quirks & How to Avoid Them

"Garbage in, garbage out." —Anonymous

SPICE is a dependable simulation engine, yet it has a handful of idiosyncrasies that can trip up even experienced users. In this article we’ll focus on the subtle file‑format and circuit‑topology rules that SPICE enforces, not on bugs that produce incorrect results. Many of these quirks were specific to SPICE 2g6, but they can still surface in newer releases.

A Proper File Start

Every SPICE netlist must begin with a non‑component line—typically a title, comment, or a blank line. If the first line is a component card, SPICE will halt with a “serious error” message, often misattributing the problem to node connections. A simple linefeed or comment is enough to satisfy the parser.

The final .end card must be written without an end‑of‑line character. After typing .end, stop the cursor immediately after the “d” and do not press [Enter]. Otherwise SPICE will report a “missing .end card” error, which does not affect the simulation itself but clutters the output.

Include Node 0

Node 0 is the reference ground for all voltage statements. Every valid netlist must contain node 0; otherwise SPICE cannot resolve the voltage scale. For example, a DC analysis will list voltages relative to node 0, as in:

node voltage node voltage ( 1) 15.0000 ( 2) 0.6522

Here node 1 is 15 V above ground, and node 2 is 0.6522 V above ground.

Don’t Leave Circuits Open

Open circuits—particularly open voltage sources—break SPICE’s ability to find a current path. When connecting a voltage source to the input of a dependent source (e.g., an op‑amp model), insert a high‑value resistor (often called rbogus) to provide a minimal load and keep the simulation running.

Avoid Undead Voltage/Inductor Loops

SPICE treats inductors as short circuits and capacitors as open circuits during DC analysis. Consequently, uninterrupted loops of inductors or voltage sources, or series capacitors without a DC path, cause the solver to fail. Typical offending patterns include:

netlist l1 2 4 10m l2 2 4 50m l3 2 4 25m

netlist v1 1 0 dc 12 l1 1 0 150m

netlist c1 5 6 33u c2 6 7 47u

To remedy this, insert a low‑resistance shunt for inductors and a high‑resistance shunt for capacitors. For example:

original netlist l1 2 4 10m l2 2 4 50m l3 2 4 25m

fixed netlist rbogus1 2 3 1e-12 rbogus2 2 5 1e-12 l1 3 4 10m l2 2 4 50m l3 5 4 25m

The rbogus resistors are essentially shorts (1 pΩ), ensuring the inductor loop no longer appears as a perfect short to the solver. For capacitors:

original netlist c1 5 6 33u c2 6 7 47u

fixed netlist c1 5 6 33u c2 6 7 47u rbogus 6 7 9e12

A 9 TΩ shunt keeps the DC path without affecting the AC behavior.

Measuring Current in SPICE

Voltage probes are straightforward—just reference the two nodes. Current probes, however, require a voltage source reference. If your circuit lacks such a source, insert a zero‑voltage “bogus” source to anchor the measurement:

c1 4 7 22u vbogus 6 4 dc 0 .print ac i(vbogus)

The AC analysis still applies, so the zero‑voltage source does not alter the simulation.

Note that SPICE assigns current polarity opposite to the conventional direction for a DC source. In a simple series circuit:

example v1 1 0 r1 1 2 5k r2 2 0 5k .dc v1 10 10 1 .print dc i(v1) .end

SPICE reports –1 mA because current leaving the negative terminal of v1 is considered negative. Reorienting the zero‑voltage source can force a positive reading if desired.

Fourier Analysis Tips

When running a Fourier (frequency‑domain) analysis, always print or plot the target waveform; otherwise SPICE will pause and abort after showing the “initial transient solution.” For pulse sources that generate square waves, supply a realistic rise and fall time. An ideal square wave (instantaneous edges) incorrectly introduces even harmonics in SPICE’s Fourier transform.

AC Analysis Configuration: Curves, Points, and Frequency Sweep Settings Verified SPICE Netlists & Example Circuits

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