JTAG Connectors, Pinouts, and Commercial Interfaces: A Practical Guide

Learn about the interfaces and connectors used to implement JTAG.

In earlier discussions we explored the foundational IEEE 1149.1 standard, focusing on the Test Access Port (TAP) that governs the TAP state machine and boundary‑scan operations. While the logical aspects are critical, designers must also master the physical layer—connectors, pinouts, and the array of commercial JTAG interfaces available today. This article bridges that gap with a hands‑on perspective.

JTAG Connectors

There is no single universal connector for JTAG. Most boards employ standard male headers—0.1" or finer pitch—to expose the required signals. The TAP itself needs only four or five pins (TDI, TDO, TCK, TMS, and optionally nTRST), but any external interface must also supply power, ground, and may provide additional utilities such as system reset or voltage reference.

Although the community has not converged on a single standard, several header configurations are widely adopted:

• ARM JTAG 20 (20‑pin 0.1" shrouded)
• ARM JTAG 14 and TI JTAG 14 (14‑pin 0.1" or 0.05")
• STDC14 (STMicroelectronics), OCDS 16‑pin (Infineon, PDF)
• CoreSight 10 & 20, MIPI 34, Mictor 38
• Segger’s J‑Link and J‑Trace connectors, which closely mirror ARM JTAG 20

Figure 1 illustrates the most common male header shapes and pitches used for JTAG connections.

Figure 1. Common headers for JTAG interfaces.

The pinout details for these various connectors are summarized in Figure 2. Standard JTAG signals (TDI, TDO, TCK, TMS, nTRST) coexist with SWDIO, SWCLK, and SWO for ARM’s Serial Wire Debug. Additional pins—such as nSRST for full system reset and VTREF for target‑side voltage reference—enable advanced debugging capabilities and level shifting.

Figure 2. Pinouts of key JTAG interfaces on 0.1" shrouded male headers.

Commercial JTAG Interfaces

Hardware vendors offer a spectrum of JTAG probes, from open‑source solutions to premium industrial tools:

• Black Magic Probe (BMP) – an open‑source ARM JTAG interface backed by 1BitSquared and Black Sphere Technologies, widely supported by community firmware.
• Segger J‑Link – the industry standard, retailing under $100 with an education license and $400–$1,000 for commercial models. The more powerful J‑Trace targets industrial deployments at $1,700–$2,500.
• Vendor‑specific probes: STMicroelectronics’ STLINK series (V2, V3SET), Microchip’s Atmel‑ICE, NXP’s S32 Debug Probe, and others.
• FPGA download cables: Xilinx Platform Cable II, Intel’s FPGA Download Cable II (formerly Altera’s USB‑Blaster II), primarily used for bitstream programming.

Internally, a typical low‑end probe comprises:

• A microcontroller that orchestrates TAP communication.
• A USB interface, either built‑in or via an FTDI‑style chip.
• Level‑shifting circuits to match target logic levels.
• Switching and pull‑up controls for signal integrity.

Most cost is driven by sophisticated firmware that unlocks full Arm CoreSight features, as exemplified by the publicly available Black Magic Probe hardware and software on GitHub.

Conclusion

We have examined the physical layer of JTAG—from connector standards and pinouts to the commercial probes that bring the technology into the lab and production floor. The next logical step is a deeper dive into the Arm CoreSight architecture and its debug interface (ADI), including the growing popularity of Serial Wire Debug as a JTAG alternative.