Accelerating CPU‑FPGA Co‑Design: A Practical Flow for Software Developers

Recently, Brian Bailey convened a round‑table that culminated in the two‑part article Supporting CPUs + FPGAs. Experts debated the evolving reality of systems that fuse FPGAs with CPUs, spotlighting how fresh design flows empower software developers to bring CPU‐plus‐FPGA platforms to market faster.

Introduction
The surge of artificial intelligence, the explosion of connected devices, and the acceleration of data‐center workloads all point to one common driver: software developers seeking speed. Low‐latency links between FPGAs and CPUs, coupled with the modest power envelopes of modern FPGAs, make hybrid CPU‐FPGA systems a natural choice for demanding performance. Yet the underlying complexity of FPGA technology often stalls developers.

High‐Level Synthesis (HLS) tools have advanced significantly, easing the mapping of C/C++ into hardware. Still, they are primarily IP‐centric and fall short on system‐level decisions—balancing software versus hardware tasks, choosing between pipelined or parallel execution, tuning data granularity, or selecting optimal communication mechanisms.

What software engineers need is a unified design flow that feels like a standard software IDE but delivers hardware‐aware feedback. Recent commercial solutions have begun to close this gap by abstracting low‐level details while retaining the control developers demand. These tools are grounded in the System‐Level Design philosophy outlined in ESL Models and Their Application.

Understanding the System‐Level Design Flow
System‐Level Design operates at higher abstraction, validating, refining, and integrating system components before implementation. Most designers start at the algorithmic level, writing C/C++/SystemC, MATLAB, Simulink, or LabVIEW models that capture the full system behavior.

We focus on a C/C++‐centric flow (see Figure 1). The first stage—application profiling—identifies which functions or loops could benefit from hardware acceleration. Next, the target CPU/FPGA platform is specified (e.g., ARM‐Cortex‐A53 + FPGA) and its parameters (clock, cache, interconnects) are configured. Finally, the profiled tasks are mapped between software and hardware, culminating in an executable architecture.

Figure 1. Typical system‐level design flow for CPU/FPGA (Source: Space Codesign Systems, Inc.)

The second block of Figure 1 covers architecture optimization—sometimes called architectural exploration or performance verification—shown in more detail in Figure 2.

Figure 2. Architecture optimization process (Source: Space Codesign Systems, Inc.)

Three key estimators feed this stage:

• Hardware estimation evaluates the impact of moving C/C++ code onto the FPGA, breaking down resource usage, loop latency, and power. It relies on HLS outputs.
• Software estimation measures CPU‐side metrics—processor load, task switching, cache misses—complementing the hardware view.
• Data‐transfer estimation models interfaces (memory‐mapped or streaming), capturing bus latency, throughput, queue depth, and memory footprint.

Aggregated results populate a database, enabling developers to verify whether system‐level goals are met. Architectures that satisfy the criteria move forward; otherwise, further optimization iterations are triggered.

The final block of Figure 1 concerns architecture implementation: high‐level designs are translated into FPGA bitstreams using vendor tools such as Xilinx Vivado or Intel Quartus Prime, producing a fully synthesized and testable system ready for deployment.

System‐Level Optimization
The absence of automated, end‐to‐end optimization tools has long been a bottleneck in FPGA‐based computing. The complexity of balancing multiple design dimensions makes manual exploration tedious, even for seasoned designers.

Figure 3 illustrates a typical optimization workflow for an image‐processing application comprising six C/C++ functions deployed on a Zynq‐7000 platform. Eight candidate architectures are considered, but time‐to‐market constraints demand a rapid selection of the best compromise between performance, area, and power.

Figure 3. Architecture exploration with system‐level decisions highlighted (Source: Space Codesign Systems, Inc.)

Commercial solutions such as Xilinx’s SDSoC/SDAccel, Falcon Computing’s Merlin Compiler, and Space Codesign’s SpaceStudio now provide end‐to‐end support. They mirror the flow in Figures 1 and 2 while injecting automated decision logic:

• SDSoC estimates latencies for hardware kernels and characterizes data transfer on the target platform, then benchmarks against a pure‐software run.
• Merlin Compiler applies source‐to‐source transformations driven by four pragmas, plus implicit compiler passes that boost pipelining and parallelism.
• SpaceStudio constructs a virtual platform (VP) that simulates the entire system, integrating hardware‐generated latencies and offering non‐intrusive profiling of both software and hardware tasks.

A View of the Commercial Ecosystem
Figure 4 presents a layered view of the ecosystem surrounding CPU/FPGA platform design. The top layer shows algorithmic entry points; the middle layer hosts tools that support system‐level optimizations from C/C++; the bottom layer contains vendor synthesis tools that produce bitstreams. Representative CPU/FPGA platforms are illustrated at the base.

Figure 4. Commercial ecosystem for CPU/FPGA platforms (Source: Space Codesign Systems, Inc.)

Table 1 lists key commercial automation tools employed in CPU/FPGA platform design.

Table 1. Commercial automation tools (*Note: A list is proposed in this review)

Conclusion
Democratizing CPU‐plus‐FPGA development is the ultimate objective, enabling a broader swath of software developers to harness hardware acceleration. Just as the software industry evolved from assembly to Python and Swift over five decades, FPGA programming is undergoing a similar maturation. The rise of system‐level tools like SpaceStudio, SDSoC, and Merlin Compiler signals a pivotal shift—yet full automation and seamless optimization across compilers remain future milestones.

Guy Bois, Ing., PhD is the Founder of Space Codesign Systems and a Professor in the Department of Software and Computer Engineering at Polytechnique Montréal. With extensive R&D experience alongside industry leaders—STMicroelectronics, Grass Valley, PMC Sierra, Design Workshops Technologies, and Cadabra Systems—Guy’s expertise in hardware/software co‐design led to the commercialization of SpaceStudio and the founding of Space Codesign Systems Inc.