Enhanced Retention in TaO/HfO and TaO/AlO RRAM: A Self‑Rectifying Switching Model

Background

NAND flash technology is approaching its scaling limits, making vertical RRAM (VRRAM) with minimal film stacks, high yield, and no cross‑coupling a promising solution for ultra‑dense memory [1,2,3]. The 1TnR 3‑D architecture enables ultralow bit cost in compact arrays [4,5,6]. Recent work has shifted RRAM operation toward low‑current, defect‑trapping, vacancy‑modulating, or interface‑type switching mechanisms [7,8,9], yet retention failures linked to oxygen‑vacancy migration remain unresolved [3,10]. Filamentary‑type retention studies propose various models to explain losses [11,12,13], suggesting a shift in switching mechanisms could improve endurance. Prior studies of TaO/HfO_x devices have shown nonlinearity of ~40, endurance >1000 cycles, and 85 °C data retention [6,7]. Achieving stable retention at low current levels, however, remains a challenge. This letter introduces a retention model based on the Arrhenius method for two defect‑trapping devices, highlighting the role of the AlO_x layer in enhancing retention through dense bonding.

Methods

TaO/HfO_x and TaO/AlO_x devices were fabricated on 8‑in. Si/thermal‑oxide substrates. Bottom electrodes (TiN) were deposited by PVD, patterned, and etched via conventional lithography. Post‑etch cleaning employed O₂/H₂O plasma at 180 °C, forming a thin TiON oxidation layer on TiN. Switching layers of HfO_x and AlO_x were deposited by ALD using HfCl₄-H₂O and TMA-H₂O precursors at 300 °C and 250 °C, respectively. A TaO capping layer was then added by low‑temperature plasma oxidation (LTPO) at 0.2 Å/s, providing an internal self‑compliance resistor. Top electrodes (TiN) were deposited by PVD. Figure 1 illustrates the layer stack and thicknesses for both device types. After patterning, a low‑temperature oxide (250 °C) was deposited for passivation, followed by standard back‑end processing for contacts and pads.

Cell schematic with thickness details for a TaO/HfO_x and b TaO/AlO_x devices. Both stacks use LTPO‑deposited TaO and plasma‑oxidized TiON interfacial layers.

Results and Discussion

The electrical performance was evaluated with an HP4156C semiconductor parameter analyzer. Figures 2a and 2b show the J–V characteristics for TaO/HfO_x and TaO/AlO_x cells, respectively, across three device areas (0.1, 0.56, and 25 µm²). All devices started in the HRS, were programmed to LRS with a positive bias, and then reset to HRS with a negative bias. The J–V curves exhibit consistent current density across cell sizes, indicating uniform field‑driven programming and confirming defect‑trapping switching behavior. The LRS and HRS resistances scale inversely with area (Fig. 2c, 2d), reinforcing the current‑density‑controlled switching mechanism. TaO/AlO_x devices require slightly higher set (4–4.5 V) and reset (–1.5 to –2.5 V) voltages than TaO/HfO_x (3–4 V, –0.5 to –1.5 V), reflecting the higher energy barrier in the AlO_x layer.

Current density vs. voltage for a TaO/HfO_x and b TaO/AlO_x devices; resistance vs. area for c TaO/HfO_x and d TaO/AlO_x devices (read at 2 V). Each point averages 10 devices with standard deviation.

Retention behavior was assessed at 85 °C and 1 V. Figures 3a and 3b reveal that LRS degrades more noticeably than HRS in both device types, yet TaO/AlO_x shows superior LRS stability. Over time, both HRS and LRS drift toward the initial resistance state (IRS), as highlighted by dashed lines in the plots. Figure 3c and 3d illustrate that baking TaO/AlO_x at 150 °C for 48 h and TaO/HfO_x at 120 °C for 120 h restores the LRS to its initial condition, underscoring the role of oxygen‑ion/vacancy recombination in retention loss.

Resistance variation over time for a TaO/HfO_x and b TaO/AlO_x at 85 °C (1 V). Post‑baking LRS restoration shown in c TaO/AlO_x (150 °C/48 h) and d TaO/HfO_x (120 °C/120 h).

Retention times were extracted using the Arrhenius method. By analyzing the LRS resistance ratio over time (30–150 °C) and extrapolating to 10³× the initial LRS, we estimated retention times of 10⁶ s at 150 °C and ~2 × 10⁸ s (≈5 years) at room temperature for TaO/AlO_x devices. Both TaO/HfO_x and TaO/AlO_x share the same activation energy of 0.38 eV, indicating that the TaO capping layer dominates the vacancy‑ion recombination process. The AlO_x layer’s higher atomic density and shorter Al–O bond length reduce oxygen‑ion mobility, creating a higher diffusion barrier that extends retention.

a Resistance ratio vs. baking time for various temperatures in TaO/AlO_x devices (average initial R = 179 MΩ at 2 V). b Estimated retention time (×10³) vs. 1/kT; extracted activation energies are 0.38 eV for both device types. c Schematic of oxygen diffusion barriers in HfO_x vs. AlO_x with TaO capping.

The retention mechanisms differ between filamentary and defect‑trapping RRAM. In filamentary devices, lateral vacancy diffusion governs rupture, whereas defect‑trapping devices exhibit longitudinal diffusion parallel to the electric field, making retention sensitive to bias polarity. Figures 5a and 5b show on‑bias retention: a positive bias prolongs LRS, while a negative bias accelerates degradation. At ±100 mV, on‑bias effects are negligible, likely due to band offsets at TiON–HfO_x, TiON–AlO_x, and TiN–TaO junctions. A 500 mV positive bias on TaO/AlO_x produces no observable degradation.

On‑bias resistance ratio vs. stress time for a TaO/HfO_x and b TaO/AlO_x devices at room temperature.

Conclusions

Comparative analysis of TaO/HfO_x and TaO/AlO_x self‑rectifying RRAM reveals that the AlO_x switching layer delivers higher switching voltages and markedly improved LRS thermal stability. The enhanced retention arises from a higher oxygen‑diffusion barrier rather than changes in activation energy. The activation energy (0.38 eV) is governed by the TaO resistive layer’s ion de‑trap process, while the dense AlO_x film suppresses vacancy diffusion, extending LRS retention. The proposed retention‑loss schematic, supported by on‑bias experiments, offers valuable guidance for designing low‑current, long‑retention, self‑rectifying RRAM for next‑generation high‑density memory.