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Encoder Fundamentals: Designing 2‑to‑1 and 7‑Segment Binary Encoders

What Is an Encoder?

An encoder is a combinational circuit that converts a set of input signals into a binary‑coded output. It is the logical inverse of a decoder. In practice, encoders are used to reduce the number of signals required to represent a set of inputs, which simplifies downstream processing and improves system reliability.

2‑to‑1 Line Encoder

To illustrate the concept, let’s derive the truth table for a simple 2‑to‑1 line encoder by reversing a 1‑to‑2 decoder. The decoder truth table is:

D1D0A
010
101

Inverting this relationship gives the encoder truth table:

D1D0A
00
010
101
11

When both inputs are active (the last row), the output is undefined. In many applications, this situation is handled by adding sequential logic to detect and flag multiple simultaneous activations, ensuring reliable operation.

Encoder Design Applications

A common real‑world application is the binary‑to‑7‑segment display encoder. The seven segments (labeled D6 through D0) must be activated to render decimal digits on a 7‑segment display. The truth table for a 4‑bit binary input (I3…I0) is shown below:

I3I2I1I0D6D5D4D3D2D1D0
00001110111
00010010010
00101011101
00111011011
01000111010
01011101011
01101101111
01111010010
10001111111
10011111011

Entries that correspond to non‑existent decimal digits (e.g., binary 1011 and above) can be treated as don’t‑care conditions, allowing the logic to be simplified. Using Karnaugh maps, the minimized equations for each output are derived as follows:

Encoder Fundamentals: Designing 2‑to‑1 and 7‑Segment Binary Encoders Encoder Fundamentals: Designing 2‑to‑1 and 7‑Segment Binary Encoders

The resulting simplified equations are summarized below:

Encoder Fundamentals: Designing 2‑to‑1 and 7‑Segment Binary Encoders Encoder Fundamentals: Designing 2‑to‑1 and 7‑Segment Binary Encoders

Resulting Circuit Diagram

Implementing the equations with standard logic gates yields the following schematic:

Encoder Fundamentals: Designing 2‑to‑1 and 7‑Segment Binary Encoders

Corresponding Ladder Diagram

For PLC applications, the ladder logic equivalent is also provided:

Encoder Fundamentals: Designing 2‑to‑1 and 7‑Segment Binary Encoders

Related Worksheet

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