home Manufacturing Technology Manufacturing Equipment
Industrial manufacturing
Industrial Internet of Things | Industrial materials | Equipment Maintenance and Repair | Industrial programming |
home  MfgRobots >> Industrial manufacturing >  >> Industrial programming >> Verilog

Verilog Priority Encoder: Reliable 4‑Input 8‑Bit Selector

Design

  
  
module pr_en ( input [7:0] a,
               input [7:0] b,
               input [7:0] c,
               input [7:0] d,
               input [1:0] sel,
               output reg [7:0] out);

   always @ (a or b or c or d or sel) begin
      if (sel == 2'b00)
         out <= a;
      else if (sel == 2'b01) 
         out <= b;
      else if (sel == 2'b10)
         out <= c;
      else 
         out <= d;
   end
endmodule

Hardware Schematic

Testbench

  
  
module tb_4to1_mux;
   reg [7:0] a;
   reg [7:0] b;
   reg [7:0] c;
   reg [7:0] d;
   wire [7:0] out;
   reg [1:0] sel;
   integer i;
   
   pr_en    pr_en0 (   .a (a),
                           .b (b),
                           .c (c),
                           .d (d),
                           .sel (sel),
                           .out (out));

   initial begin
      sel <= 0;
      a <= $random;
      b <= $random;
      c <= $random;
      d <= $random;

      for (i = 1; i < 4; i=i+1) begin
         #5 sel <= i;
      end

      #5 $finish;
   end
endmodule

Verilog

  • C Language
  • VHDL
  • Verilog
  • MATLAB
  • Python
  • Java
    1. Verilog Basics: Designing Your First AND Gate
    2. Encoder Fundamentals: Designing 2‑to‑1 and 7‑Segment Binary Encoders
    3. Master Verilog: Complete Tutorial for Digital Circuit Design
    4. Mastering Verilog Syntax: Key Rules & Best Practices
    5. Verilog Module Basics: Structure & Syntax
    6. Understanding Verilog Assign Statements: Continuous Signal Assignment Explained
    7. Mastering Verilog Concatenation: A Practical Guide
    8. Understanding Verilog Always Blocks: Syntax & Sensitivity Lists
    9. Verilog Initial Blocks: Purpose, Syntax, and Non‑Synthesizable Use
    10. Mastering Verilog Generate Blocks: Dynamic Module Instantiation & Conditional Design