Common‑Gate JFET Amplifier: Design, Operation, and Applications

RELATED WORKSHEETS:

• JFET Amplifiers Worksheet

What Is a Common‑Gate JFET Amplifier?

The common‑gate (CG) configuration is one of the three classic JFET topologies (common‑source, common‑drain, common‑gate). In the CG stage the gate is the common terminal, the source is the input, and the drain is the output. This arrangement provides low input impedance, high output impedance, and a negative voltage gain that can reach 10–20× for typical discrete JFETs.

How It Works

A voltage change at the source modulates the gate‑to‑source voltage (V_GS). The JFET’s drain current, I_D, follows the equation I_D = I_DS (1 – V_GS/V_P)². Because the drain is at a higher potential than the source, the output voltage at the drain is the product of I_D and the drain resistor (R_D), giving a negative voltage gain of approximately –R_D/(R_S + r_o).

Typical Biasing Scheme

The gate is often tied to ground through a high‑value resistor or a bias network to maintain V_GS ≈ 0 V. A source resistor (R_S) establishes the bias point and provides negative feedback, improving linearity. A small DC bias (e.g., 0.2 V) may be applied to the gate via a voltage divider if a slightly negative V_GS is desired for higher gain.

Advantages and Use Cases

• Low input impedance (<1 kΩ), ideal for driving high‑impedance RF front‑ends.
• High output impedance, useful for voltage‑to‑current conversion.
• Excellent frequency response—common‑gate stages can exceed 100 MHz with proper layout.
• Excellent noise performance when the source resistor is chosen to match the input source impedance.

Example Design

Components: 2N5457 JFET, V_D = 12 V, R_D = 10 kΩ, R_S = 1 kΩ.

Bias point: V_GS ≈ –0.2 V, I_D ≈ 2 mA. Voltage gain ≈ –10. Bandwidth > 10 MHz with a 10 pF load.

Design Tips

1. Select a JFET with a suitable pinch‑off voltage (V_P) and transconductance (g_m) for the target frequency.
2. Minimize parasitic capacitances by using a short‑lead layout and low‑capacitance PCB material.
3. Use a proper heat‑sink or thermal pad if operating near the JFET’s maximum drain current.
4. Verify the linearity by checking the third‑order intercept point (IP3) in a two‑tone test.

Further Resources

For a hands‑on design exercise, download the JFET Amplifiers Worksheet and work through the bias calculations, gain prediction, and simulation.