Synopsys Unveils Complete HBM3 IP Suite for Multi‑Die Systems, Boosting Bandwidth to 921 GB/s

Synopsys has introduced the industry’s first fully integrated HBM3 IP stack, encompassing controller, PHY, and verification IP tailored for 2.5D multi‑die package systems. Built on a silicon‑proven HBM2E foundation, DesignWare’s HBM3 controller and PHY leverage Synopsys’ interposer expertise to deliver high memory bandwidth—up to 921 GB/s—while maintaining low power consumption and minimal design risk.

The accompanying verification ecosystem includes coverage‑driven verification IP, pre‑built HBM3 memory models for ZeBu emulation, and the HAPS prototyping system, streamlining the path from IP to SoC validation. Synopsys’ 3DIC Compiler further accelerates development with a fully integrated architectural exploration, implementation, and system‑level analysis workflow.

DesignWare HBM3 controller IP offers versatile configuration options, advanced RAS features such as ECC, refresh management, and parity, and is engineered to minimize latency and safeguard data integrity across a wide range of HBM3 applications.

Available in a 5‑nm process, the DesignWare HBM3 PHY IP supports up to 7200 Mbps per pin, enhances power efficiency, and provides four dynamic frequency‑scaling states. Its optimized micro bump array and flexible interposer trace‑length support allow designers to position the PHY without compromising performance.

Synopsys Verification IP employs a next‑generation native SystemVerilog universal verification methodology, enabling seamless integration into existing testbenches, rapid test coverage expansion, and accelerated time‑to‑first‑test. Off‑the‑shelf HBM3 memory models for ZeBu emulation and the HAPS prototyping platform further empower RTL and software validation at higher performance levels.

“Synopsys continues to meet the evolving design and verification needs of data‑intensive SoCs with high‑quality memory interface IP for HBM3, DDR5, and LPDDR5,” says John Koeter, Synopsys’ Senior Vice President of Marketing and Strategy for IP. “Our complete HBM3 IP and verification suite lets designers tackle growing bandwidth, latency, and power demands while accelerating verification closure—all from a single, trusted partner.”

The DesignWare HBM3 controller, PHY, and verification IP, along with ZeBu emulation models, HAPS prototyping, and the 3DIC compiler, are now available. The company has received strong endorsements from industry leaders.

Mark Montierth, VP and GM for High‑Performance Memory & Networking at Micron, notes, “HBM3 will deliver the memory bandwidth essential for the next generation of high‑performance computing and AI systems. Our partnership with Synopsys accelerates ecosystem development for ultra‑high‑bandwidth, energy‑efficient HBM3 products with unprecedented performance.”

Samsung Electronics’ Kwangil Park, SVP of Memory Product Planning, emphasizes the growing bandwidth demands across AI, HPC, and graphics. “As the world’s leading memory chip maker, Samsung is committed to supporting ecosystem readiness and advancing HBM to meet these needs. Synopsys is a pioneer in the HBM ecosystem and a valued partner.”

SK Hynix highlights its continued investment in next‑generation memory technologies, including HBM3 DRAMs, to support AI and graphics workloads. The company will collaborate with Synopsys to offer fully tested, interoperable HBM3 solutions that maximize performance, capacity, and throughput for shared customers.

Yutaka Hayashi, VP of the Data Center & Networking Business Unit at Socionext, explains, “Our collaboration with Synopsys, leveraging HBM2E IP on a 5‑nm process and an integrated full‑system multi‑die design platform, will now extend to the new DesignWare HBM3 IP and verification solutions. This will enable our customers to achieve higher memory performance and capacity in SoCs that adopt the upcoming HBM3 specification.”