Xilinx Launches Zynq RFSoC DFE – A High‑Performance, Power‑Efficient Hard IP Solution for 5G Radios

Xilinx has unveiled the Zynq RFSoC Digital Front End (DFE), a dedicated hard‑IP solution engineered for 5G New Radio (NR) deployments. Building on the robust Zynq UltraScale+ architecture, the new DFE extends the RFSoC family with high‑performance, low‑power compute blocks that handle the most demanding 5G NR and legacy 4G workloads in next‑generation radio units (RUs).

5G’s promise of unprecedented speed, ultra‑low latency, and massive connectivity introduces complex design challenges. While mobile device manufacturers have a growing palette of 5G chipsets, the varied performance and power requirements across use cases – from enhanced mobile broadband to ultra‑reliable low‑latency communication (URLLC) and massive machine‑type communication (mMTC) – demand specialized, adaptable solutions.

3GPP Release 15 laid the groundwork for 5G NR focused on enhanced mobile broadband (eMBB). Release 16 expanded the spectrum to include URLLC and mMTC, enabling critical applications such as industrial automation, remote surgery, and smart‑city deployments. Future releases (17, 18, and beyond) will further add NR‑MIMO, dynamic spectrum sharing, and application‑specific enhancements.

Network function virtualization and network slicing empower operators to provision dedicated, high‑performance slices tailored to each application. However, realizing this flexibility hinges on radios that combine the right mix of performance, flexibility, and power efficiency.

“As the 5G market evolves, integrated RF solutions must stay adaptable to meet future standards,” said Liam Madden, Executive Vice President and General Manager of Xilinx’s Wired and Wireless Group. “The Zynq RFSoC DFE delivers the optimal balance between that adaptability and fixed‑function IP.”

The Zynq RFSoC DFE embeds hard‑IP cores that implement the core functions required in 5G RU signal paths (Figure 1). Because the hard‑IP DFE core occupies a smaller footprint than the equivalent soft‑IP implementation in the earlier Zynq RFSoC Gen 3, the new device supports more DFE cores, boosting compute performance while cutting power consumption. Xilinx estimates the DFE can achieve at least 2× the DFE processing performance per watt compared to a fully utilized Zynq RFSoC Gen 3.

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Figure 1. The Zynq RFSoC DFE hard IP supports a broad range of processing capabilities required for 5G NR as well as legacy 4G radios. (Source: Xilinx)

At the same time, developers can customize the signal path by bypassing hard‑IP blocks or inserting proprietary logic into the fabric (Figure 2).

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Figure 2. The Zynq RFSoC DFE functional architecture combines hard IP, logic fabric and processor subsystem. (Source: Xilinx)

Zynq RFSoC DFE design documentation and support are available to early‑access customers, with shipments slated for the first half of 2021. For more information, visit the Xilinx RFSoC DFE product page. Xilinx will also provide additional details during its 5G virtual event on November 18–19.