Imec & GlobalFoundries Reveal 2900 TOPS/W Processor‑in‑Memory Chip for Ultra‑Efficient AI

Revolutionary Analog Compute

Imec and GlobalFoundries have demonstrated a processor‑in‑memory chip that can achieve energy efficiency up to 2900 TOPS/W, roughly two orders of magnitude above today’s commercial solutions. The design leverages analog computing inside SRAM, built with GlobalFoundries’ 22 nm fully‑depleted silicon‑on‑insulator (FD‑SOI) process.

Imec’s analog in‑memory compute (AiMC) will be available to GlobalFoundries customers as a feature on the 22FDX platform.

Imec’s AnIA test chip, mounted on the PCB used for measurement, can reach 2900 TOPS/W (Image: Imec)

Analog Compute Explained

Analog computing, or processor‑in‑memory, is a proven technique already adopted by commercial AI accelerators from Mythic, Syntiant, Gyrfalcon, and others. It eliminates the costly data shuttling between memory and processor by performing multiply‑accumulate operations directly within a memory array.

Each memristor cell is programmed to an analog conductance proportional to a neural‑network weight. A voltage proportional to the input activation drives the cell, and the resulting current represents the product of activation and weight. The current sum on each bit‑line yields the matrix‑vector multiplication required by neural networks, which can then be read out via an analog‑to‑digital converter.

“In practice, we can use ReRAM, MRAM, Flash, or DRAM—our goal is to identify the best option for each application and fine‑tune the technology,” said Diederik Verkest, program director for machine learning at Imec.

Imec’s AnIA Test Chip

Built on GlobalFoundries’ 22 nm FD‑SOI, AnIA features a 512k‑cell SRAM array, 1024 DACs, and 512 ADCs across 4 mm². It can perform roughly 500 000 computations per cycle with 6‑bit activations (plus sign bit), ternary weights, and 6‑bit outputs.

“We can deliver matrix‑vector multiplication results at multiple supply voltages—0.8 V and 0.6 V—without compromising accuracy. Lower voltages dramatically reduce power consumption, which is critical for energy‑constrained inference on the edge,” explained Ioannis Papistas of Imec’s machine‑learning group.

On the CIFAR‑10 object‑recognition task, AnIA’s accuracy dropped only one percentage point compared to a similarly quantised baseline. At 0.8 V, the chip achieved 1 050–1 500 TOPS/W for 23.5 TOPS; at 0.6 V, it reached 5.8 TOPS and 1 800–2 900 TOPS/W.

Energy efficiency comparison: Imec’s AnIA vs. other AI accelerators (click to enlarge) (Image: Imec)

From Lab to Mass Production

“This innovation is destined for mainstream adoption,” said Hiren Majmudar, VP and GM of GlobalFoundries’ computing business unit. “We see partners already in the post‑production phase with validated silicon. We anticipate analog‑compute silicon to reach production by year‑end or early next year, and to appear in the mass market no later than 2022—potentially sooner.”

GlobalFoundries is integrating Imec’s AiMC technology into its 22FDX platform, enabling ultra‑low‑power AI accelerators. The FD‑SOI process supports operation down to 0.5 V with 1 pA/µm standby leakage. The 22FDX+AiMC feature is currently under development on GlobalFoundries’ 300 mm line at Fab 1 in Dresden, Germany.

Imec’s machine‑learning program will push toward 10 000 TOPS/W (10 TOPS below 100 mW) for always‑on smart sensors and wearables. Future work will focus on shrinking compute cells and exploring emerging memory devices as next‑generation platforms.

>> This article was originally published on our sister site, EE Times.