FPGA Hardware Resources for High‑Performance Embedded Systems

Editor’s Note: As advanced algorithms continue to emerge for smart product designs, developers often find themselves struggling to implement embedded systems that can meet the associated processing demands. FPGAs can deliver the required performance, but designing with FPGAs has long been considered the domain of FPGA programming experts. Today, however, the availability of more powerful FPGAs and more effective development environments has made FPGA development broadly accessible. In this excerpt from Chapter 4 of *Architecting High‑Performance Embedded Systems*, the author offers a comprehensive review of FPGA devices, implementation languages, and the development process, as well as a detailed walkthrough of how to start implementing FPGAs in your own design.
1: Hardware resources (this article)
2: Implementation languages
3: Development process
4: Building a project
5: Implementation

Adapted from *Architecting High-Performance Embedded Systems*, by Jim Ledin.

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Developing Your First FPGA Program

This chapter begins with a discussion on the effective use of FPGA devices in real‑time embedded systems and continues with a description of the functional elements contained within standard FPGAs. It introduces the range of FPGA design languages—including Hardware Description Languages (HDLs), block‑diagram methods, and popular software programming languages such as C and C++—and provides an overview of the FPGA development process. The chapter concludes with a complete example of an FPGA development cycle, from system‑requirements statement to a fully functional system implemented on a low‑cost FPGA development board.

After completing this chapter, you will understand how FPGAs can be applied in real‑time embedded system architectures, the key components of an FPGA IC, the programming languages used to design FPGA algorithms, and the step‑by‑step sequence for developing an FPGA‑based application. You will also walk through a full FPGA development example on a low‑cost board using free FPGA software tools.

We will cover the following topics:

• Using FPGAs in real‑time embedded system designs
• FPGA implementation languages
• The FPGA development process
• Developing your first FPGA project

Technical requirements

The files for this chapter are available at https://github.com/PacktPublishing/Architecting-High-Performance-Embedded-Systems.

Using FPGAs in real‑time embedded system designs

As outlined in the Elements of FPGAs section of Chapter 1, a typical FPGA device contains a large number of lookup tables, flip‑flops, block RAM elements, DSP slices, and other components. While it is useful to understand the detailed capabilities of each component, the most critical consideration is that a specific FPGA part number contains a finite number of each resource, and a design cannot exceed those limits when targeted at that particular model.

It is more productive to view the development process from the perspective of the embedded system’s statement of requirements. You can begin by targeting a model that comfortably meets those requirements. As the design progresses, you may encounter a resource limit or discover that a required feature is missing. At that point, selecting a more capable target and continuing development is straightforward. Conversely, if you find that the chosen FPGA contains excess resources, moving to a smaller part can reduce cost, pin count, package size, and power consumption.

Switching the targeted FPGA within the same family is typically seamless, with design artifacts fully reusable. Switching families or vendors may require additional effort. The key takeaway is that the specific model need not be chosen at the outset; focus first on validating the FPGA as a viable solution, then select a suitable vendor and device family.

Example projects in this book use Xilinx’s Vivado family of tools. While a Vivado license is required for some Xilinx families, the Artix‑7 devices used here are supported for free. The Artix‑7 combines high performance, low power, and reduced system cost. Similar families and tool suites are available from other vendors.

FPGA development is an involved process that requires a range of analysis and design data. To keep the discussion concrete, we will use Vivado throughout this book. Once you master these techniques, you can apply them to other vendors’ tools.

The following sections discuss key differentiating features of FPGA families and models, including block RAM capacity, I/O signal types, specialized on‑chip resources, and the presence of embedded processor cores.

Block RAM and Distributed RAM

Block RAM implements dedicated memory regions within an FPGA. A memory region is specified by its bit width (typically 8 or 16 bits) and depth (number of storage locations). Total block RAM is usually expressed in kilobits (Kb) and varies across families and models.

Many FPGAs also provide distributed RAM, built from lookup‑table logic to form small 16‑bit segments. These can be combined into larger blocks when needed. Distributed RAM is ideal for temporary storage of intermediate results, whereas block RAM is used for caches or I/O buffers.

Block RAM can be single‑port or dual‑port. Dual‑port RAM, with two read/write ports, is especially useful for bridging subsystems that operate at different clock speeds, enabling data transfer without interference.

Block RAM can operate in FIFO mode, providing signals for full, empty, almost full, and almost empty states. Careful control of write and read operations prevents data loss or corruption.

FPGA I/O Pins and Associated Features

FPGA I/O pins support a variety of high‑speed standards. During design, developers assign functions to specific pins and configure each pin’s interface standard. Signals are either single‑ended or differential.

Single‑ended signals reference ground and historically used TTL/CMOS ranges. Modern FPGAs support lower voltage ranges—LVTTL (0–3.3 V) and LVCMOS variants (1.2, 1.5, 1.8, 2.5, 3.3 V)—reducing power consumption and improving speed. High‑speed single‑ended standards include HSTL and SSTL.

Differential signaling, which uses a pair of pins, is preferred for high‑data‑rate links because common‑mode noise is largely canceled. Differential standards include HSTL, SSTL, and LVDS. LVDS, introduced in 1994, delivers a constant 3.5 mA current and switches direction to represent data bits. Matching the transmission line impedance (100 Ω for LVDS) to the termination impedance is essential to avoid reflections.

Specialized Hardware Resources

FPGAs often include dedicated hardware for functions that benefit from fixed, efficient implementation:

• External dynamic RAM (DRAM) interfaces, typically supporting DDR3
• Analog‑to‑digital converters
• Phase‑locked loops for generating multiple clock frequencies
• Digital signal processing MAC hardware

Dedicated hardware such as MAC units delivers performance far beyond what can be achieved with synthesized logic.

Processor Cores

Some FPGA families integrate hard processor cores—for example, Xilinx Zynq‑7000 combines an ARM Cortex‑A9 with FPGA fabric. When a design does not require a hard core, a soft processor can be instantiated from FPGA resources. Soft processors are highly configurable but typically do not match the performance of hard cores.

The next section will introduce the primary programming languages and data entry methods used to develop FPGA algorithms.

Reprinted with permission from Packt Publishing. Copyright © 2021 Packt Publishing

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Jim Ledin is the CEO of Ledin Engineering, Inc. Jim is an expert in embedded software and hardware design, development, and testing. He is also accomplished in embedded system cybersecurity assessment and penetration testing. He holds a B.S. in aerospace engineering from Iowa State University and an M.S. in electrical and computer engineering from Georgia Institute of Technology. Jim is a registered professional electrical engineer in California, a Certified Information System Security Professional (CISSP), a Certified Ethical Hacker (CEH), and a Certified Penetration Tester (CPT).

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