Embedded FPGA Design: A Complete Development Process

Editor’s Note: As advanced algorithms continue to emerge for smart product designs, developers often struggle to implement embedded systems that can meet the processing demands of these algorithms. FPGAs deliver the necessary performance, and recent advances in device capability and development environments have made FPGA design accessible to a wider range of engineers. This excerpt from Chapter 4 of *Architecting High‑Performance Embedded Systems* provides a comprehensive review of FPGA devices, implementation languages, and the development process, and offers a practical walkthrough for getting started with FPGA design.
1: Hardware resources
2: Implementation languages
3: Development process (this article)
4: Building a project
5: Implementation

Adapted from *Architecting High‑Performance Embedded Systems*, by Jim Ledin.

---

The FPGA Development Process

Across diverse application domains, FPGA development follows a common sequence of steps that guide engineers from concept to functional hardware. The following sections outline the typical workflow, highlighting key decisions and best practices.

Defining System Requirements

Successful FPGA projects begin with a clear, unambiguous definition of system functionality, operating modes, and key features. Document the intended behavior in plain language and share it with all stakeholders to achieve consensus. Include quantitative performance metrics—such as input sampling rates, output update intervals, throughput, latency, and power limits—as well as constraints on physical size, battery life, temperature range, and cost. A complete requirement set ensures that any design meeting all specifications is viable; if a technically correct solution fails for reasons like cost, the omission likely lies in the requirement phase.

Once top‑level requirements are agreed, decompose the system into coherent subsystems, each with its own functional and technical specifications. In real‑time embedded systems, the digital processing capability typically forms a dedicated subsystem with its own set of constraints.

Allocating Functionality to the FPGA

When a system’s digital processing demands exceed the capabilities of microcontrollers or processors, consider an FPGA. Architectures that benefit from high‑speed, parallel hardware are prime candidates. Even if a conventional processor could meet performance, an FPGA can offer flexibility and upgrade potential over the product’s lifecycle.

After deciding to use an FPGA, allocate the relevant processing tasks to it. Define the FPGA’s input and output interfaces, update rates, and interactions with peripheral components such as ADCs, DACs, and memory devices.

Identifying Required FPGA Features

With the FPGA’s responsibilities and interfaces defined, compile a list of mandatory device features. Consider resource requirements—logic cells, DSP blocks, memory—and power and cooling needs. Low‑cost, battery‑powered designs may use smaller devices with passive cooling, while high‑performance systems may need large FPGAs with active cooling.

Device families differ in available features; for example, some include integrated ADCs to reduce board complexity. Use the requirements to shortlist candidate families, then narrow down to specific models as resource estimates become clearer.

Implementing the FPGA Design

With a candidate device selected and functionality mapped, begin the implementation using a vendor tool suite—commonly Xilinx Vivado or Intel Quartus. The process typically starts with a top‑level design, which may be expressed as a block diagram or written directly in HDL (Verilog or VHDL) or high‑level synthesis languages such as C/C++.

Iterate through the following phases, refining the design until a working bitstream is produced:

Design Entry
Define system logic using HDL, block diagrams, or C/C++ code. These artifacts describe the intended behavior but not the physical integration.

I/O Planning
Assign I/O pins, set signal standards, and consider physical constraints like pin placement and trace length for high‑speed signals. I/O constraints, together with timing constraints, guide the synthesis process.

Synthesis
Convert HDL into a netlist that maps logic to the chosen FPGA’s resources. If constraints cannot be satisfied, synthesis fails and the design must be revisited.

Place and Route
Place the netlist’s logic elements onto specific FPGA resources while honoring constraints. Route interconnections to finalize the physical layout. The outcome is a fully specified configuration.

Bitstream Generation
Create the configuration file that loads the FPGA’s internal SRAM. This bitstream is analogous to a software executable and must be loaded on every power‑on cycle, typically from onboard flash or an external source.

After the bitstream is produced, perform thorough testing to verify functional correctness.

Testing the Implementation
Test at every stage: simulate HDL logic, validate the synthesized netlist, and run hardware‑in‑the‑loop tests on the target board. Comprehensive testing mitigates rare‑occurrence bugs that can undermine product credibility.

The next section details a hands‑on example using the Arty A7 board and the Vivado tool suite.

Reprinted with permission from Packt Publishing. Copyright © 2021 Packt Publishing

---

Jim Ledin is the CEO of Ledin Engineering, Inc. He brings deep expertise in embedded software and hardware design, development, and testing, and is a recognized authority in embedded system cybersecurity. With a B.S. in aerospace engineering from Iowa State University and an M.S. in electrical and computer engineering from Georgia Institute of Technology, Jim is a licensed professional engineer in California, a CISSP, CEH, and CPT.

---

Related Contents:

• Embedded design with FPGAs: Hardware resources
• Embedded design with FPGAs: Implementation languages
• Open‑source tools help simplify FPGA programming
• Implementing floating‑point algorithms in FPGAs or ASICs
• Leveraging FPGAs for deep learning
• Software tools migrate GPU code to FPGAs for AI applications
• FPGAs displace ASICs in Subaru Eyesight vision‑based ADAS

For more Embedded, subscribe to Embedded’s weekly email newsletter.