Getting Started with FPGA Development: Building a 4‑Bit Adder on Xilinx Artix‑7

Editor’s Note: As advanced algorithms continue to evolve, embedded designers often struggle to meet the processing demands of modern applications. Field‑Programmable Gate Arrays (FPGAs) provide the necessary performance, and recent hardware and tooling advances have made FPGA development accessible to a broader audience. This article, the fourth in a series derived from *Architecting High‑Performance Embedded Systems* by Jim Ledin, offers a hands‑on walk‑through of building a simple but complete FPGA project.

Developing Your First FPGA Project

We’ll construct a 4‑bit binary adder on a Xilinx Artix‑7 FPGA housed in a Digilent Arty A7 development board. Two board variants are available: the cost‑effective 35T model (US $129) and the more powerful 100T model (US $249). The only distinction is the FPGA variant, which influences available logic resources. The 100T is preferable for future projects that demand more resources, such as the digital oscilloscope example in later chapters.

Purchase options: Digilent Store, Amazon, and other retailers.

For this tutorial, we’ll focus on the FPGA core, four user switches, four pushbuttons, and five LEDs. The steps below cover installing the Vivado tool suite, creating a project, writing VHDL code, and loading a bitstream onto the board—both into volatile configuration memory and into onboard flash for persistent operation.

Project Overview

The design implements a 4‑bit adder. Four switches provide the first 4‑bit operand, four pushbuttons supply the second. The FPGA continuously adds these operands and displays the 4‑bit sum on four LEDs, with a fifth LED indicating the carry‑out. This straightforward design lets us concentrate on toolchain workflow rather than complex logic.

Installing Vivado

We’ll use Xilinx Vivado, available free of charge for Windows and Linux. The following instructions assume Windows; Linux installation steps are analogous.

1. Create a Xilinx user account: https://www.xilinx.com/registration/create-account.html
2. Log in at https://xilinx.com and navigate to the download page.
3. Download the Xilinx Unified Installer (Windows Self‑Extracting Web Installer). For consistency with this book, select version 2020.1; otherwise, use the latest release.
4. Run the installer (e.g., Xilinx_1_0602_1208_Win64.exe). If Windows blocks the download, choose “Install anyway.”
5. Click Next on the welcome screen.
6. Enter your Xilinx credentials and click Next.
7. Acknowledge the license agreements and click Next.
8. Choose Vitis as the product (Vitis bundles Vivado and additional tools). Click Next.
9. Accept the default component selections and click Next.
10. Select a destination directory (e.g., C:\Xilinx) and click Next.
11. Review the summary and click Install. Installation may take several minutes.

Once installed, launch Vivado from the desktop shortcut or Start menu.

Creating the Project

1. Open Vivado and click Create Project in the Quick Start pane.
2. Enter ArtyAdder as the project name, choose a directory (e.g., C:\Projects), and tick Create a subdirectory for this project. Click Next.
3. Select RTL Project and check Do not specify sources at this time. Click Next.
4. Under the Boards tab, search for “Arty” and pick Arty A7-100 or Arty A7-35 based on your hardware. Click Next.
5. Finish the wizard to create an empty project.

Adding VHDL Source Files

1. In the Sources pane, right‑click Design Sources → Add Sources….
2. Choose Add or create design sources and click Next.
3. Select Create File, name it FullAdder.vhdl, and click OK.
4. Repeat to create Adder4.vhdl, then click Finish.
5. Ignore the Define Modules dialog; click OK and confirm with Yes.
6. Open FullAdder.vhdl and paste the following code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FULL_ADDER is
  port (
    A     : in  std_logic;
    B     : in  std_logic;
    C_IN  : in  std_logic;
    S     : out std_logic;
    C_OUT : out std_logic
  );
end entity FULL_ADDER;

architecture BEHAVIORAL of FULL_ADDER is
begin
  S     <= (A XOR B) XOR C_IN;
  C_OUT <= (A AND B) OR ((A XOR B) AND C_IN);
end architecture BEHAVIORAL;

6. Open Adder4.vhdl and replace its contents with:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ADDER4 is
  port (
    A4    : in  std_logic_vector(3 downto 0);
    B4    : in  std_logic_vector(3 downto 0);
    SUM4  : out std_logic_vector(3 downto 0);
    C_OUT4: out std_logic
  );
end entity ADDER4;

architecture BEHAVIORAL of ADDER4 is
  component FULL_ADDER is
    port (
      A     : in  std_logic;
      B     : in  std_logic;
      C_IN  : in  std_logic;
      S     : out std_logic;
      C_OUT : out std_logic
    );
  end component;
  signal c0, c1, c2 : std_logic;
begin
  FULL_ADDER0 : FULL_ADDER
    port map (
      A     => A4(0),
      B     => B4(0),
      C_IN  => '0',
      S     => SUM4(0),
      C_OUT => c0
    );
  FULL_ADDER1 : FULL_ADDER
    port map (
      A     => A4(1),
      B     => B4(1),
      C_IN  => c0,
      S     => SUM4(1),
      C_OUT => c1
    );
  FULL_ADDER2 : FULL_ADDER
    port map (
      A     => A4(2),
      B     => B4(2),
      C_IN  => c1,
      S     => SUM4(2),
      C_OUT => c2
    );
  FULL_ADDER3 : FULL_ADDER
    port map (
      A     => A4(3),
      B     => B4(3),
      C_IN  => c2,
      S     => SUM4(3),
      C_OUT => C_OUT4
    );
end architecture BEHAVIORAL;

Next Steps

The following article will guide you through simulating this design, synthesizing it for the Arty board, and programming the resulting bitstream onto the FPGA.

Reprinted with permission from Packt Publishing. Copyright © 2021 Packt Publishing

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