Mastering Digital Filtering on Embedded Microcontrollers: PowerQuad’s Dual Biquad IIR Engine in the LPC55S69

Explore the most common techniques for filtering time‑domain data, and examine how the LPC55S69’s PowerQuad Dual Biquad IIR engine accelerates DSP tasks.

When working with data collected over time, the first step is often to apply a digital filter. Understanding the various filtering strategies not only improves signal quality but also frees up the CPU for other critical tasks—an essential consideration for embedded microcontrollers.

This article covers the most widely used time‑domain filtering methods and delves into the Dual Biquad IIR engine of the PowerQuad unit in the LPC55S69 MCU, a powerful DSP building block that can be leveraged in a variety of filtering scenarios.

Common Filters for Continuously Sampled Data

In a time‑domain acquisition system, samples arrive at a fixed, known rate. Time‑domain filters process these samples and produce a new signal that can be further processed or sent to a digital‑to‑analog converter (DAC). The core of any filter is its response to sine waves—altering amplitude and phase across frequencies. The collective behavior over a frequency spectrum is known as the filter’s frequency response.

Finite Impulse Response (FIR) filters are a standard approach. They generate each output sample by combining the most recent data with a history of previous samples.

Figure 1. Sample‑by‑sample filter processing using a history of the input.

One straightforward implementation stores prior samples in an array and applies the following equation:

x[n] // The most recent input
x[n-1], x[n-2] // The two previous input samples
y[n] // The next output sample

y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2]

This simple multiply‑and‑accumulate operation uses constant coefficients and a defined history length to shape the filter’s frequency response. By tuning the coefficients, the filter can act as a low‑pass, high‑pass, or band‑pass device.

While conceptually simple, FIR filters often require many past samples to achieve precise control, which can be computationally expensive on a conventional CPU—especially when the history grows.

To reduce the required history, many designs incorporate feedback, forming the basis of Infinite Impulse Response (IIR) filters:

// This example follows the naming conventions used earlier
y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]

The example above illustrates a biquad filter, a common IIR building block that can be cascaded for higher‑order responses. Fewer coefficients are needed compared to an FIR filter, but careful coefficient selection is essential to avoid instability and oscillation.

Numerous tools exist to generate optimal coefficients for standard filter designs. These “cookbooks” provide a quick path to high‑quality filters.

Figure 2. One of the many tools that automatically generate coefficients.

Using the PowerQuad IIR Biquad Engines

The LPC55S69’s PowerQuad unit offers dedicated hardware for executing IIR biquad filters. Offloading the filtering workload to this co‑processor frees the Cortex‑M33 cores to focus on application logic.

Although the filter algorithms themselves are straightforward, they can consume significant CPU cycles. The PowerQuad’s hardware is specifically optimized for filtering and other complex mathematical operations. It connects to the system via the AHB bus and the Arm® Cortex®‑M33 coprocessor interface.

Developers typically use the free, Eclipse‑based MCUXpresso IDE and the LPC55S69 SDK, which includes several PowerQuad example applications.

Figure 3. Selecting the PowerQuad digital filter example.

The “powerquad_filter” example demonstrates a range of filter configurations. The core logic resides in powerquad_filter.c, which showcases basic filter setups.

While the article introduced a Direct Form I implementation, the PowerQuad internally reorders operations into a Direct Form II structure. This arrangement eliminates the need to store both input and output histories, instead maintaining a single intermediate state vector v[n].

Several AHB registers hold the state and coefficients necessary for configuring the PowerQuad’s IIR filter operations. In the SDK examples, the state is initialized via PQ_BiquadRestoreInternalState.

Once initialized, the filter processes data blocks using PQ_VectorBiquadDf2F32 in fsl_powerquad_filter.c:

/* Function processes input samples in multiples of eight. */

Figure 4. Vectorized IIR Filter Implementation

This routine transfers data from the main CPU to the PowerQuad co‑processor via the MCR instruction. The PowerQuad performs the multiply‑add operations, delivering the filtered result back to the CPU with another MCR transfer. This offloading dramatically reduces CPU load compared to executing the same algorithm on the Cortex‑M33 cores.

The Dual Biquad IIR Engine for Digital Filtering

The LPC55S69’s PowerQuad unit contains two independent biquad engines, enabling parallel or cascaded filtering operations. Configuration registers on the AHB bus set up the IIR functions, and data exchange occurs over the coprocessor interface.

The MCUXpresso SDK provides a solid starting point, though the supplied code prioritizes clarity over raw performance. Developers can further optimize by minimizing data transfers between the CPU and PowerQuad.

NXP offers an IIR Biquad Filter Design & Visualization Tool that assists in generating and visualizing filter coefficients. The NXP community page also offers in‑depth documentation on the LPC55S69’s PowerQuad unit and its capabilities.

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