Accelerating Co‑Designed SoC Development with Renode Simulators

This article demonstrates how open‑source functional simulators such as Antmicro’s Renode become indispensable in hardware‑software co‑design.

Embedded systems are evolving rapidly, and next‑generation SoCs are growing in complexity. According to Semico Research, this complexity drives longer design cycles and higher costs. To meet customer demands for new features, stronger security, and better performance, manufacturers must adopt “whole‑stack” co‑design—simultaneously evolving hardware, firmware, operating systems, and toolchains. However, without robust simulation tools, co‑design can stall, extending timelines and inflating budgets.

Open‑source functional simulators like Renode can bridge this gap. They allow hardware and software teams to prototype, test, and iterate in parallel, dramatically shortening the design cycle. Below we explore a real‑world case study with Dover Microsystems and illustrate how Renode delivers tangible benefits.

Where Software Simulators Can Fall Short

Dover Microsystems’ CoreGuard® technology exemplifies the need for a flexible, multi‑architecture simulator. CoreGuard is a hybrid cybersecurity solution that protects embedded processors from network‑based attacks. Its design relies on a sentry processor that monitors every instruction executed by the host CPU, ensuring compliance with a set of security, safety, and privacy rules called micropolicies. Because the sentry must keep pace with the host processor, CoreGuard demands tight integration between hardware and software, high performance, low power, and minimal memory overhead.

The hardware team at Dover used a standard SystemVerilog toolchain to prototype CoreGuard on RISC‑V SoCs. Meanwhile, the software team needed to start development before any silicon existed. Initially, they relied on Spike, the RISC‑V ISA simulator available on GitHub. Spike posed two major limitations:

1. It lacks realistic peripheral models, forcing the team to add UARTs, storage, and other devices manually.
2. Spike is RISC‑V‑only, while Dover’s early customers targeted both RISC‑V and ARM platforms.

These challenges highlighted the need for a flexible, multi‑architecture simulator that could model peripherals without extensive custom code.

How Renode Addresses Key Co‑Design Needs

Antmicro, a leader in open‑source technology and services, developed Renode to meet exactly these requirements. Renode is a hierarchical, modular simulation framework that runs unmodified firmware across complex systems—including multi‑node, heterogeneous, MCU‑level, and Linux‑capable configurations. Its core design treats cores and peripherals as interchangeable building blocks that can be connected through standard interfaces, mirroring real SoC construction.

Figure 1. Example of a simulated RISC‑V SoC.

Each component—CPU, bus, or peripheral—exposes properties and APIs that enable rapid system construction via configuration files and scripts. This approach keeps Renode’s codebase lean and lowers the learning curve. Antmicro’s commercial support further accelerates adoption and integration.

Using Renode, Dover engineers can:

• Switch seamlessly between ARM and RISC‑V integration environments.
• Prototype SoCs at varying fidelity levels, from reference models to customer‑specific designs.
• Translate hardware specifications into firmware models, enabling software testing while hardware remains under development.

How Renode Significantly Decreased Dover’s Design Cycle

CoreGuard’s hybrid nature required parallel development of hardware and software. Renode enabled a tightly coupled workflow illustrated in Figure 2.

Figure 2. Dover’s integrated hardware‑software development process.

As the hardware team began SystemVerilog implementation, the software team modeled new blocks in C#, Renode’s native language. Firmware could then be written and executed against these models, with results validated on an FPGA emulator once the silicon was ready.

Renode’s dual‑fidelity approach offered distinct advantages:

• Low‑fidelity simulation—abstracting CoreGuard hardware—facilitated rapid micropolicy debugging, demo creation, and customer SDK distribution.
• High‑fidelity simulation—accurate hardware modeling—enabled boot‑process development, peripheral debugging, memory‑map exploration, and even HDMI firmware testing before silicon availability.

Beyond these operational benefits, Renode empowered Dover to explore hardware/software trade‑offs—such as instruction‑rate matching, metadata memory usage, and power consumption—without the delays inherent in a “first‑hardware‑then‑software” approach. This flexibility directly contributed to a shorter design cycle and lower development costs.

To learn more about how Renode can streamline your co‑design projects, visit renode.io. For a live demonstration of CoreGuard’s protection capabilities, request a demo today.

This article was co‑authored by Michael Gielda, VP Business Development and co‑founder of Antmicro.

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