Dual Functionality of V/SiOx/AlOy/p++Si Devices: Selector and Memory Switching Controlled by Compliance Current

Abstract

This study demonstrates that a single V/SiO_x/AlO_y/p⁺⁺Si resistive memory cell can operate as either a selector or a memory element simply by tuning the compliance current limit (CCL). When a low CCL of 1 µA is applied during a positive forming step, the device exhibits unidirectional threshold switching, attributable to a metal‑insulator transition (MIT) in the VO_x layer formed at the vanadium electrode. A higher CCL of 30 µA, however, induces bipolar resistive switching governed by the formation and rupture of a conductive filament in the SiO_x layer. A 1.5‑nm AlO_y layer with high thermal conductivity reduces off‑current in both modes, and temperature‑dependent measurements reveal a high‑energy barrier (0.463 eV) in the low‑resistance state (LRS), enhancing nonlinearity at lower CCLs. The coexistence of these two functions provides flexibility for designing cross‑point arrays that combine selector and memory capabilities.

Background

Resistive random‑access memory (RRAM) is a leading candidate for next‑generation non‑volatile memory due to its ultrafast switching, low power, multilevel storage, high scalability, and compatibility with 3‑D stacking ^1–25. RRAM can bridge the performance gap between DRAM and SSD, serving as storage‑class memory (SCM). However, a critical challenge remains: sneak‑current paths in dense cross‑point arrays. Selector devices with nonlinear current–voltage (I–V) characteristics are essential to suppress these parasitic currents ^26–35. Various selector concepts—complementary resistive switching, tunnel barriers, Ag‑based threshold switching, diode‑type selectors, ovonic threshold switching, and metal‑insulator transitions—have been explored ^26–43. VO_x is a prototypical MIT material, while SiO₂ is widely used as a passivation layer. Si‑rich SiO_x (x < 2) offers CMOS compatibility and can serve as a resistance‑change layer in RRAM ^44–55, enabling filamentary switching or valence‑change mechanisms. The present work introduces a V/SiO_x/AlO_y/p⁺⁺Si cell that exhibits both selector and memory behavior depending solely on the applied CCL, leveraging a silicon bottom electrode for improved series resistance and filament control.

Methods

The device stack was fabricated on a Si substrate. First, BF₂ ions were implanted at 40 keV and a dose of 5 × 10¹⁵ cm^–2 to heavily dope the Si bottom electrode (BE), followed by 1050 °C annealing for 10 min to repair lattice damage, yielding a sheet resistance of 30.4 Ω/□. A 1.5‑nm AlO_y layer was deposited by atomic layer deposition (ALD) using H₂O and trimethylaluminum. A 5.5‑nm SiO_x layer was then formed by plasma‑enhanced chemical vapor deposition (PECVD) at 300 °C using 5 % SiH₄/N₂ (160 sccm), N₂O (1300 sccm), and N₂ (240 sccm). A 50‑nm vanadium (V) top electrode (TE) of 100 µm diameter was sputtered (Ar, 30 sccm) and capped with a 50‑nm Al layer to prevent oxidation. Electrical measurements were performed with a Keithley 4200‑SCS semiconductor parameter analyzer and a 4225‑PMU ultra‑fast I–V module at room temperature.

Results and Discussion

The cross‑sectional TEM image (Fig. 1b) confirms the amorphous V, SiO_x, and AlO_y layers atop the single‑crystalline Si BE, with thicknesses of 5.5 nm and 1.5 nm, respectively. XPS analysis shows SiO_x stoichiometry x = 0.88 and AlO_y y = 1.33, indicating a slightly oxygen‑deficient SiO_x conducive to resistive switching. Unidirectional threshold switching (Fig. 2a) appears after a positive forming step under a 1 µA CCL. The device exhibits a sharp turn‑on at a threshold voltage V_th between 1.08 and 1.82 V and returns to the off‑state at a hold voltage V_hold between 0.12 and 0.54 V over 100 cycles. Temperature dependence shows threshold behavior up to 55 °C, but it vanishes at 85 °C, confirming VO_x MIT as the switching mechanism. Transient measurements (Fig. 2d) reveal a high current during the write pulse that decays immediately after pulse removal, characteristic of selector operation. The AlO_y layer’s high permittivity and thermal conductivity significantly suppress off‑current (<100 pA at 1 V) compared to VO_x selectors. Bipolar resistive switching (Fig. 3a) emerges when the same device is formed with a 30 µA CCL. The device switches from HRS to LRS upon a positive reset pulse and returns to HRS after a negative set pulse. Normalized conductance (G_N) remains close to 1 at zero bias across temperatures, ruling out Schottky, Fowler–Nordheim, and space‑charge‑limited conduction. Instead, the LRS exhibits semiconducting behavior, implying that the filament resides in SiO_x rather than in the VO_x layer. Analysis of the ln(I) versus 1000/T plot yields an activation energy of 0.463 eV, and a hopping distance of 5.17 nm, supporting a hopping conduction model for the filament. A Poole–Frenkel emission contribution is also observed (see Supplementary). The high‑energy barrier and fine filament at low CCLs increase nonlinearity and reduce sneak currents. Figure 4a–d illustrate how varying the CCL (5 µA, 30 µA, 1 mA) modulates the LRS I–V curve and nonlinearity. Lower CCLs suppress current at low bias, increasing the nonlinearity ratio (I(V_READ)/I(½V_READ)). This intrinsic nonlinearity arises from the bulk properties of SiO_x and the AlO_y barrier. Using an equivalent circuit model, the read margin (ΔV) for a cross‑point array scales with word‑line count; at 10 % read margin, arrays of 10 × 10 (5 µA CCL) and 5 × 5 (1 mA CCL) are feasible. While higher read voltage (1 V) yields greater nonlinearity than 0.5 V, it also increases static power.

Conclusions

The V/SiO_x/AlO_y/p⁺⁺Si cell demonstrates dual functionality: a low‑CCL (≤1 µA) selector driven by VO_x MIT and a high‑CCL (≥5 µA) memory cell governed by SiO_x filament formation. The 1.5‑nm AlO_y layer provides high selectivity (10⁴) and low off‑current. Lower CCLs increase nonlinearity, enabling larger cross‑point arrays with reduced sneak currents.

Abbreviations

ALD

Atomic layer deposition

BE

Bottom electrode

CCL

Compliance current limit

CRS

Complementary resistive switching

DRAM

Dynamic random‑access memory

HRS

High‑resistance state

I–V

Current–voltage

LRS

Low‑resistance state

MIT

Metal‑insulator‑transition

OTS

Ovonic threshold switching

PECVD

Plasma‑enhanced chemical vapor deposition

P‑F

Poole‑Frenkel

RRAM

Resistive random‑access memory

SCLC

Space‑charge‑limited current

SCM

Storage class memory

SPA

Semiconductor parameter analyzer

SSD

Solid‑state‑drive

TE

Top electrode

TEM

Transmission electron microscopy

V

Vanadium