Scalable Fabrication of Gate‑Controlled UV Sensors Using Self‑Assembled ZnO Nanowire Networks

Abstract

We present a straightforward, low‑temperature process for creating arrays of gate‑controlled ultraviolet (UV) photodetectors based on zinc oxide (ZnO) nanowire (NW) network field‑effect transistors (FETs). The method combines molecularly patterned substrates, selective NW assembly via a controlled pulling technique, and a mild heat treatment at 300 °C. The resulting devices exhibit n‑type behavior, an on‑off ratio of 10⁵, transconductance of 47 nS, and carrier mobility of 0.175 cm² V⁻¹ s⁻¹. UV photoresponsivity is tunable by gate bias, reaching 8.6 × 10⁵ at V_g = −55 V and V_ds = 7 V. The process delivers a 90 % device yield and avoids high‑temperature or vacuum steps, paving the way for large‑scale, cost‑effective UV sensor production.

Background

One‑dimensional nanomaterials such as ZnO nanowires offer high surface area, directional charge transport, and scalable fabrication, making them attractive for optoelectronic devices [1,2]. ZnO, with a direct bandgap of 3.37 eV and a large exciton binding energy (60 meV), is environmentally benign, abundant, and inexpensive [10,11]. It has been successfully integrated into LEDs, lasers, solar cells, photodetectors, and chemical sensors [12–30]. However, conventional ZnO NW photodetectors require complex patterning, high‑temperature growth, or etching steps that limit yield and increase cost. Recent strategies, such as laser‑induced selective growth [34,35] or hydrothermal growth on localized heaters [36], are energy‑intensive and unsuitable for large‑area manufacture. There is a clear need for a simple, scalable approach that preserves device performance while enabling precise control of channel geometry.

In this study, we demonstrate a highly reproducible fabrication route that employs self‑assembly of ZnO NWs onto OTS‑patterned substrates, followed by a low‑temperature anneal. The process yields a dense, percolating NW network with controllable width and thickness, and produces UV photodetectors with excellent electrical characteristics and gate‑tunable photoresponse.

Methods

ZnO NW Network FET Fabrication

Commercial ZnO NWs (length 2–3 µm, diameter 200 nm) were dispersed at 1 wt% in dichlorobenzene (DCB) via 3 s sonication. Silicon wafers with 300 nm SiO₂ were patterned using AZ 5214E photoresist. The exposed SiO₂ was functionalized with 1:500 v/v OTS in hexane for 3 min, creating non‑polar OTS domains. Subsequent acetone treatment removed the resist, exposing the polar SiO₂ regions. The substrate was then dipped into the NW suspension and withdrawn at a controlled speed (0.5–10 mm min⁻¹) while stirring at 100 rpm to prevent aggregation. Van der Waals forces guided the NWs to assemble exclusively on the polar SiO₂ areas, leaving the OTS regions clean. Ti/Al (10/300 nm) source–drain electrodes were deposited by thermal evaporation and defined via lift‑off.

Heat Treatment

Samples were annealed in a 1 Torr Ar atmosphere. The temperature ramped to 110 °C for 3 min, held for 10 min to evaporate solvents, then to 300 °C for 3 min, held for 10 min to improve inter‑NW contacts, and finally cooled to room temperature over 1 h.

Electrical and Photoresponse Measurements

I–V and gate sweeps were performed on a probe station with a Keithley 4200A‑SCS analyzer. V_ds spanned 0–7 V; V_g ranged from −60 to +60 V. Device tests were conducted at 23 ± 1 °C and 35 ± 1 % RH. UV illumination (365 nm, 350 µW cm⁻²) was applied using a handheld lamp while measuring V_ds = 7 V.

Results and Discussion

Figure 1 illustrates the fabrication workflow: OTS patterning, selective NW assembly, electrode deposition, and annealing. We fabricated 100 devices on a 4‑inch wafer, achieving a 90 % yield. Channel dimensions were 6 µm (length) × 20 µm (width). Figure 2a shows a representative NW network; SEM images confirm selective assembly on SiO₂ patterns of 5, 10, and 20 µm width (Fig. 2b). AFM analysis (Fig. 2c) revealed that pulling speed directly controls NW density and network thickness. At 0.5 mm min⁻¹, the density was 1.21 NW µm⁻² and the network height reached ~400 nm, whereas at 10 mm min⁻¹ the density dropped to 0.09 NW µm⁻² and the network approached the percolation threshold.

Electrical measurements before annealing (Fig. 3a) showed that slower pulling speeds increased channel conductance, attributed to higher NW connectivity. Gate‑dependent I–V curves (Fig. 3b,c) displayed classic n‑type FET behavior with an on‑off ratio of 5.6 × 10² (from 3 pA to 556 nA) and a transconductance of 47 nS at V_g = −30 V. The device yield and resistance distribution shifted with pulling speed: 28.2 ± 4 MΩ average resistance and 92 % yield at 0.5 mm min⁻¹ versus 877 ± 280 MΩ and 78 % yield at 2 mm min⁻¹.

Annealing at 300 °C produced a dramatic three‑order‑of‑magnitude drop in resistance (Fig. 4b) and increased the on‑off ratio to 2 × 10⁵. The transconductance remained essentially unchanged, confirming that the anneal improves inter‑NW contact without altering intrinsic material properties. Mobility calculations yielded 0.175 cm² V⁻¹ s⁻¹, comparable to values reported for similar ZnO NW arrays [49].

Under UV illumination, the devices exhibited a pronounced gate‑dependent photoresponse (Fig. 5). The photocurrent ratio I_light/I_dark reached 8.6 × 10⁵ at V_g = −55 V and V_ds = 7 V, with the ratio decreasing as V_g increased. A linear correlation between the initial on‑off ratio and the photoresponsivity (Fig. 5d) demonstrates that devices with higher on‑off ratios yield greater sensitivity. The recovery time varied with gate bias: −60 V yielded a 52 s fall time, whereas +60 V yielded 141 s, highlighting the role of the electric field in recombination dynamics.

Compared to other ZnO NW photodetectors, our devices achieve comparable or superior photoresponsivity (~2 × 10⁴ under 60 V gate bias) without high‑temperature or vacuum steps. The gate‑controllable response adds a valuable tuning knob for applications requiring dynamic sensitivity adjustment.

Conclusions

We have established a scalable, low‑cost fabrication route for ZnO NW network FETs that serve as gate‑controlled UV sensors. The process eliminates chemical or plasma etching, uses a mild 300 °C anneal, and yields 90 % functional devices with on‑off ratios of 10⁵, transconductance of 47 nS, and mobility of 0.175 cm² V⁻¹ s⁻¹. Photoresponsivity is adjustable via gate bias, achieving peak values of 8.6 × 10⁵. This methodology offers a clear pathway toward commercial UV sensor technologies.