Cu‑Doped LaAlO₃ RRAMs: Lower Forming Voltage, Higher On/Off Ratio, and Improved Yield via 600 °C Annealing

Introduction

Resistive random‑access memory (RRAM) is a leading candidate for next‑generation non‑volatile memory, offering a simple metal–insulator–metal (M‑I‑M) stack, low power consumption, high scalability, rapid operation, and multi‑state storage [1]. The dielectric layer critically determines RS performance, and high‑k oxides such as HfO₂ [2], Al₂O₃ [3], and ZrO₂ [4] have been widely explored. Lanthanum‑based oxides stand out for their high dielectric constant, wide bandgap, and excellent thermal stability [5], and recent reports demonstrate low‑voltage switching, large resistance window, long endurance, and strong reproducibility in La‑based RRAMs [6, 7].

Atomic layer deposition (ALD) provides precise thickness control, uniformity, and CMOS compatibility, making it a popular method for depositing La‑based dielectrics [8]. However, the high‑quality films often require large forming voltages, which can lead to high failure rates, reduced on/off ratios, and poor endurance [9]. To overcome these limitations, device‑level engineering such as ion implantation [10], dopant diffusion [11], or nanocrystal insertion [12] is essential.

While dopant and nanocrystal strategies have improved RS in traditional high‑k materials (HfO₂ [13], ZrO₂ [14]), similar work has not yet been reported for La‑based RRAMs. Here, we fabricate a Cu‑embedded LaAlO₃ device with the structure Cu/LaAlO₃/Cu/LaAlO₃/Pt, and investigate how Cu doping and subsequent annealing affect performance and switching mechanisms.

Methods

The device stack Cu/LaAlO₃/Cu/LaAlO₃/Pt is illustrated in Fig. 1. Fabrication began with a 2‑inch SiO₂/Si wafer. A 100‑nm Pt/10‑nm Ti bottom electrode was deposited by electron‑beam evaporation. LaAlO₃ layers (~10 nm, La/Al = 3:1) were grown at 300 °C in a Picosun R‑150 ALD reactor using La(i‑PrCp)₃, Al(CH₃)₃, and O₃ as precursors. A ~2‑nm Cu interlayer was deposited by electron‑beam evaporation at 0.1 Å s⁻¹. After the second LaAlO₃ deposition, rapid thermal annealing (RTA) at 600 °C for 30 s in N₂ was applied to selected samples. The top electrode comprised 10 nm Au/150 nm Cu, patterned by lithography to produce devices ranging from 50 × 50 µm² to 250 × 250 µm². Control samples included S1: Au/Cu/LaAlO₃/Pt (unannealed) and S2: Au/Cu/LaAlO₃:Cu/Pt (unannealed), while S3: Au/Cu/LaAlO₃:Cu‑NC/Pt was the annealed, Cu‑NC‑containing device.

Schematic of the Cu‑embedded LaAlO₃ device (Cu/LaAlO₃/Cu/LaAlO₃/Pt)

Cu distribution was examined by X‑ray photoelectron spectroscopy (XPS), while cross‑sectional microstructure was revealed by transmission electron microscopy (TEM). RS characteristics were measured with an Agilent B1500A analyzer under a 1 mA compliance current to protect the devices during forming and set operations.

Results and Discussion

XPS depth profiling (Fig. 2) shows that Cu 2p signals are confined to the interlayer in unannealed S2, but after RTA (S3) Cu atoms are uniformly distributed throughout the LaAlO₃ stack, confirming that high‑temperature annealing drives Cu diffusion and nanocrystal formation.

XPS Cu 2p spectra for S2 and S3 after 30 s, 60 s, and 90 s Ar ion etching.

TEM images (Fig. 3) reveal a pristine multilayer in S2, with 2–6 nm Cu nanoparticles emerging after the first LaAlO₃ deposition. Post‑annealing (S3) further homogenizes Cu distribution, forming ~25‑nm‑thick LaAlO₃ layers embedded with discrete Cu‑NCs.

TEM images of Cu‑embedded RRAMs: (a) S2 cross‑section, (b) HRTEM of S2, (c) S3 cross‑section, (d) HRTEM of S3.

Forming curves (Fig. 4) demonstrate a dramatic voltage reduction from ~12 V (S1) to ~7 V (S2/S3) with Cu insertion. The initial resistance drops from 2.51 × 10¹² Ω (S1) to 2.65 × 10⁶ Ω (S2) and rises again to 2.83 × 10¹² Ω after annealing (S3). This behavior reflects the influence of Cu‑induced defects on dielectric breakdown and the subsequent annealing‑driven defect anneal.

Forming process of the three La‑based RRAM variants.

Bipolar I–V sweeps over 100 cycles (Fig. 5a–c) confirm stable RS in all devices, but S3 shows the smoothest curves and the highest reset‑stop voltage (≈ −1.4 V), underscoring its superior reliability. Endurance tests (Fig. 5d–f) reveal that S3 achieves an on/off ratio of ~10⁶, far exceeding the ~10⁴ ratio of S1 and S2, and displays a markedly reduced resistance variation (σ/μ ≈ 1.0 for HRS, 0.74 for LRS). These metrics demonstrate that Cu diffusion and nanocrystal formation during annealing mitigate filamentary randomness and improve uniformity.

Typical bipolar I–V curves and endurance of S1, S2, and S3.

Statistical analysis (Fig. 6) confirms that annealed S3 has the narrowest spread in both resistance states and switching voltages, confirming improved uniformity. The reset voltage distribution in S3 narrows from 0.20 V to 0.13 V, and the set voltage spread reduces from 0.82 V to 0.45 V.

Cumulative probability of HRS/LRS and set/reset voltages.

Retention tests (Fig. 7) show that S3 maintains a stable HRS/LRS ratio (~10³) for >10⁴ s at room temperature, confirming nonvolatile behavior. Yield measurements (Fig. 8) further indicate that Cu insertion boosts the 10‑cycle bipolar yield from <30 % (S1) to >70 % (S3), with smaller devices achieving even higher yields, consistent with Joule‑heat‑assisted filament formation.

Retention behavior of La‑based RRAMs at room temperature.

10‑cycle bipolar SET/RESET yield for S1, S2, and S3.

Further investigation of S3 (Fig. 9) reveals both unipolar and bipolar RS, consistent with electrochemical metallization (ECM) driven by Joule heating. The LRS exhibits ohmic conduction (slope ≈ 1), while the HRS follows a space‑charge‑limited current (SCLC) mechanism with distinct low‑, intermediate‑, and high‑field regimes, indicative of defect‑mediated transport. Temperature dependence (Fig. 10) confirms metallic behavior in the ON state (α = 1.03 × 10⁻³ K⁻¹) and semiconducting OFF state, supporting the CF formation model.

RS behavior of S3: (a) I–V sweep in both polarities, (b) log–log I–V plot and ln(I/V)–V¹⁄² fitting.

(a) Area dependence of HRS/LRS; (b) Temperature dependence of HRS/LRS.

Figure 11 schematically depicts the RS cycle: Cu oxidation at the TE, Cu²⁺ migration under the field, reduction at the BE, and filament growth along Cu‑NC pathways. Reverse bias induces Joule‑heated filament dissolution, restoring the OFF state. This cycle illustrates how Cu diffusion and nanocrystal formation underpin the observed RS.

RS mechanism of Cu/LaAlO₃:Cu‑NC/Pt devices (a) initial state; (b,c) set process; (d) ON state; (e) reset process.

Conclusion

Embedding a Cu nanolayer into LaAlO₃, followed by 600 °C annealing, markedly enhances La‑based RRAM performance. Lower forming voltage, higher on/off ratio, improved uniformity, and superior yield are achieved due to Cu diffusion and Cu‑NC formation. The RS mechanism is governed by Cu conductive filaments, space‑charge‑limited current, and Joule heating. This approach provides a practical route to tailor La‑based RRAM characteristics and warrants further exploration of the underlying physics.

Availability of Data and Materials

The datasets supporting the conclusions of this manuscript are included within the manuscript.

Abbreviations

ALD

atomic layer deposition

RRAM

resistive random access memory

NCs

nanocrystals

M‑I‑M

metal‑insulator‑metal

RS

resistive switching

High‑k

high dielectric constant

BE

bottom electrode

RTA

rapid thermal annealing

TE

top electrode

XPS

X‑ray photoelectron spectroscopy

DC

direct current

CFs

conductive filaments

HRS

high resistance state

LRS

low resistance state

SCLC

space charge limited current