IBM Research Team Wins 2017 Innovation Award for Pioneering InGaAs/SiGe CMOS Technology

IBM scientists in Zurich have been honored with the 2017 Compound Semiconductor Industry Innovation Award, recognizing five years of breakthrough research that integrates high‑mobility materials into silicon CMOS to scale devices below 7 nm.

Across the spectrum—from mobile phones to the Internet of Things to cloud infrastructure—there is a persistent tension between power consumption and performance. IBM’s team proposes a solution centered on two pillars: scaling technology nodes and adopting new, high‑mobility materials.

The award‑winning work is the first demonstration of an Indium Gallium Arsenide (InGaAs)/Silicon‑Germanium (SiGe) CMOS process on a silicon (Si) substrate using 300 mm wafer‑scale fabrication suitable for high‑volume production. This hybrid integration offers a clear path to improve the power/performance trade‑off for digital circuits beyond the 7 nm node.

Leveraging selective epitaxy, the team produced functional inverters and dense 6‑transistor SRAM arrays—core components of digital CMOS—directly on silicon. Dr. Lukas Czornomaz, a lead scientist on the project, explained: “This technology is expected to deliver 25 % better performance at the same power, or double the battery life of mobile devices while maintaining their performance.”

Join @LCzornomaz at @CS_Conference he presents Hybrid IIIV/SiGe technology for CMOS beyond https://t.co/iUiqSDPqJr pic.twitter.com/G2e0fOTDid

— IBM Research (@IBMResearch) February 25, 2016

Disclosed at the recent VLSI Technology conference, this first‑of‑its‑kind achievement follows a series of key demonstrations presented at IEDM and VLSI Symposium meetings over the past four years. The core challenge—simultaneously growing high‑quality InGaAs crystals, fabricating high‑performance InGaAs field‑effect transistors on insulator, and integrating them with SiGe devices on a single silicon wafer—has been overcome.

Unlike earlier approaches, IBM’s solution delivers the fundamental building blocks of digital circuits at relevant dimensions and marks a major milestone toward a manufacturable hybrid InGaAs/SiGe CMOS technology. The method relies on three key innovations: selective growth of high‑quality InGaAs‑on‑Insulator regions, fabrication of InGaAs finFETs with a physical gate length (L_g) of 35 nm and strong device performance, and processing of functional 6‑transistor SRAM cells with an area of approximately 0.4 µm².

Beyond digital logic, this technology paves the way for low‑cost RF and photonic circuits that combine III‑V materials with silicon CMOS—an attractive prospect for next‑generation Internet‑of‑Things devices.

“While there is still much work to be done, we have demonstrated that our design works and that it’s manufacturable,” said Dr. Czornomaz.

Moving forward, the team will continue to refine the technology for mass production and explore its application in integrated RF communication and photonic devices alongside silicon CMOS.

This research was funded by the European Union under Grant Agreements No. 619325 (FP7‑ICT‑COMPOSE3), No. 619326 (FP7‑ICT‑III‑V‑MOS), and No. 628523 (FP7‑IEF‑FACIT).