Silicon Labs Unveils 5G‑Ready Si539x Jitter Attenuators with Fully Integrated Reference

Silicon Labs has expanded its Si539x jitter attenuator family, introducing devices that embed a fully integrated reference crystal. The result is a reliable, high‑performance solution that streamlines PCB layout for next‑generation high‑speed networking.

Designed to meet the exacting reference‑clock demands of 100/200/400/600/800 G systems, the new Si539x devices deliver more than a 40 % margin over the stringent jitter specifications of 56 G PAM‑4 SerDes found in cutting‑edge Ethernet switch SoCs, PHYs, FPGAs, and ASICs. They also lay the groundwork for emerging 112 G SerDes technologies.

The integrated crystal is pre‑screened for activity dips and has undergone rigorous temperature, shock, vibration, and aging tests, ensuring consistent operation across a wide environmental envelope. Its tightly specified construction mitigates temperature‑induced drift, even in fan‑heated systems.

Because the crystal is housed within an advanced package, the Si539x series offers superior immunity to acoustic emissions (AE)—the subtle noise generated by PCB thermal gradients or mechanical stress. External crystals are more susceptible to AE‑induced frequency error, whereas the Si539x’s protected design maintains a steady frequency response over time.

For architects building high‑port‑count optical and Ethernet line cards, the integrated reference shrinks the PCB footprint by over 35 %. Removing the need for a separate crystal keeps‑out area allows denser clock routing and a simpler design process.

Each Si539x device can generate any frequency between 100 Hz and 1 028 MHz on up to 12 differential clock outputs, eliminating the need for separate clock generators or buffers. This “clock‑tree‑on‑chip” approach removes additive jitter from discrete clock trees, delivering clean, low‑jitter timing throughout the system.