DARPA Awards Contracts to Four Teams for ASIC Accelerators in Fully Homomorphic Encryption

The Defense Advanced Research Projects Agency (DARPA) has awarded contracts to four teams to develop ASIC accelerators for fully homomorphic encryption (FHE) as part of its Data Protection in Virtual Environments (DPRIVE) program. The four contracts, awarded to Duality Technologies, Intel, SRI International, and Galois, range from $11.5 million to $15 million, with Intel’s award amount undisclosed.

Fully homomorphic encryption is the 'Holy Grail' of encryption technologies

The 3.5‑year DPRIVE program aims to enable computation on FHE‑encrypted data within one order of magnitude of the compute time of current unencrypted operations. Fully homomorphic encryption allows algorithms to run directly on encrypted data, producing a decrypted result that matches what would have been obtained from unencrypted data.

Traditional encryption schemes require the key to be shared so that data can be decrypted for processing, creating a vulnerability. In contrast, FHE does not require key sharing; the data remains encrypted from end to end.

Commercially available homomorphic encryption typically supports only addition of encrypted numbers. Fully homomorphic encryption permits any mathematical operation on encrypted data. Since its inception in 2009, the technology has remained largely impractical due to its computational intensity.

"A computation that would take a millisecond on a standard laptop could take weeks on a conventional server running FHE today," said DARPA program manager Tom Rondeau.

"Fully homomorphic encryption requires thousands of FFTs sequentially, and 500‑order polynomials with double‑precision floating‑point coefficients," explained Cornami CEO Wally Rhines. "This demands performance far beyond today’s CPUs and GPUs."

Wally Rhines (Image: Cornami)

Although not part of the DPRIVE program, Cornami has pivoted from AI acceleration to FHE, asserting that the field currently has no competitors. The company’s goal aligns with DARPA’s: to bring FHE to practical performance levels.

Usable FHE would transform AI development. Most AI training occurs in the cloud, but privacy concerns hinder the use of sensitive data in sectors such as finance and healthcare. With ASIC accelerators for FHE, companies could upload encrypted data, train models in the cloud, and download only decrypted results—ensuring data privacy while enabling collaborative learning across institutions.

Technical Challenges

Each DPRIVE team must build a hardware‑and‑software stack that brings FHE performance close to that of unencrypted workloads. DARPA requires the designs to be flexible, scalable, and programmable.

One core strategy is the exploration of large arithmetic word sizes (LAWS). Current CPUs use 64‑bit words, but FHE benefits from much larger word lengths because the signal‑to‑noise ratio improves with word size, allowing more operations before the noise threshold is exceeded. Teams are expected to investigate word sizes up to several thousand bits.

Verifying LAWS circuits is especially challenging. As word size grows, the state space becomes enormous; prior verification attempts timed out at 256 bits. Cryptographic circuits demand rigorous proof of correctness, necessitating full‑circuit verification.

Additional research will target novel memory management, flexible data structures, and efficient programming models.

Contract Recipients

Duality Technologies

Duality Technologies received $14.5 million to develop a DPRIVE ASIC. The startup specializes in FHE solutions for regulated sectors such as finance and healthcare, offering its SecurePlus middleware that enables analytics on encrypted data. Duality’s team includes experts from the University of Southern California, New York University, Carnegie Mellon, SpiralGen, Drexel University, and TwoSix Labs. The accelerator will integrate with the open‑source Palisade FHE library.

Kurt Rohloff (Image: Duality Technologies)

"Hardware FHE acceleration is a matter of dimensionality and bit width," said Duality CEO Kurt Rohloff. "We handle vectorized operations with dimensions in the tens of thousands and are exploring multi‑hundred‑bit to multi‑thousand‑bit word sizes."

Intel

Intel’s DPRIVE team spans Intel Labs, design engineering, and data platforms. Intel has partnered with Microsoft to deploy the ASIC in Azure and Jedi clouds and will collaborate with international standards bodies on FHE standards. Intel claims its ASIC could reduce FHE processing time by up to five orders of magnitude, though details remain forthcoming. The company plans to evaluate the accelerator on AI training and inference workloads using FHE‑encrypted data at scale.

SRI International

SRI International, a nonprofit research institute, received $11.5 million to tackle the FHE accelerator challenge. "Creating a new hardware accelerator for FHE encrypted data requires expertise in co‑processor architectures, hardware design, verification, software, mathematics, and FHE algorithms," said SRI principal computer scientist Karim Eldefrawy. He added that the team’s expertise positions them to deliver a commercially viable solution within a few years.

Galois

Galois, a computer‑science R&D firm working with DARPA and NASA, secured a $15.3 million contract to build an FHE accelerator. The company focuses on asynchronous circuit design, enabling each computation to run at its own speed, and on a new data‑flow microarchitecture that routes data “just in time” to independent processing elements. Galois estimates a total performance improvement of 10,000× over current software‑based FHE systems, broken down into hardware acceleration, asynchronous logic, large word size operations, optimized data flow, and memory access patterns.

Timeline

DPRIVE is a 42‑month, three‑phase program. Each phase delivers performance metrics that determine progression to the next stage. Phase 1 (15 months) focuses on core logic and word‑size optimization. Phase 2 (15 months) completes the accelerator design and memory architecture. Phase 3 (12 months) delivers a fully functional, software‑programmable ASIC. The program is expected to conclude around September 2024.

— This article was originally published on EE Times.

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