Ultraviolet Irradiation Enhances Blocking Voltage of 4H‑SiC PiN Diodes: Experimental and Simulation Insights

Abstract

This study investigates the impact of 184.9 nm ultraviolet (UV) irradiation on the static performance of high‑voltage 4H‑SiC PiN diodes. Forward conduction characteristics remain virtually unchanged after exposure, whereas the reverse blocking voltage rises markedly. TCAD simulations attribute this improvement to an expanded depletion region driven by increased surface negative charge. Deep‑level transient spectroscopy (DLTS) confirms that UV‑induced deep‑level defects dominate over trapped negative charges, thereby raising the blocking voltage. These findings underscore UV irradiation as a powerful tool for tailoring SiC power device characteristics.

Introduction

Silicon carbide (SiC) is rapidly emerging as the material of choice for next‑generation high‑power, high‑temperature electronics due to its wide bandgap, exceptional critical electric field, high electron saturation velocity, and superior thermal conductivity [1–4]. SiC devices are poised to replace silicon counterparts in applications demanding voltages above 1 kV, currents exceeding 100 A, and operation temperatures above 200 °C. While unipolar SiC devices have seen significant progress, bipolar structures—particularly 4H‑SiC PiN diodes—offer additional conductivity modulation benefits that enable ultra‑high‑voltage rectification for smart grids, energy storage, and pulsed power systems [5–8].

Fabrication of SiC power devices commonly employs plasma‑based techniques such as dry etching and sputter deposition, which can introduce damage and degrade electrical performance [9,10]. Prior work has shown that high‑energy UV exposure degrades SiC MOSFETs via ion bombardment and plasma photoemission [11,12], and that pulsed UV lasers can create near‑interface oxide traps in SiC MOS structures [13]. However, the effect of UV irradiation on SiC PiN diodes remains unexplored, warranting a systematic investigation of its influence on forward and reverse characteristics.

In this work, we expose 4H‑SiC PiN diodes to 184.9 nm UV light and assess changes in forward conduction and reverse blocking voltage. TCAD simulations elucidate the role of surface charge accumulation, while DLTS measurements characterize SiO₂/SiC interface state evolution. Our combined experimental–simulation approach reveals that UV irradiation generates deep‑level defects that significantly enhance blocking voltage without compromising forward conduction.

Methods

The investigated 4H‑SiC PiN diode features a 2 µm buffer layer (1×10¹⁸ cm⁻³) and a 60 µm n‑drift layer (2×10¹⁴ cm⁻³) grown on a 4°‑off‑axis heavily doped n‑type 4H‑SiC(0001) substrate. A 2 µm p⁺ anode (2×10¹⁹ cm⁻³) caps the structure. After epitaxy, a 2.5 µm‑high, 300 µm‑diameter isolation mesa is defined via inductively coupled plasma etching (SF₆/O₂) and a double Al‑implant JTE (1×10¹⁷ cm⁻³) is introduced to mitigate edge field crowding. Activation occurs at 1650 °C for 30 min in Ar. A 40 nm SiO₂ thermal oxide (1100 °C, 3 h) follows a 1 h SiO₂ growth and HF dip to ensure a pristine surface. Ni/Ti/Al and Ni contacts (anode/cathode) are annealed at 800 °C and 1000 °C, respectively, yielding specific resistances of 1×10⁻⁵ Ω cm² (n‑type) and 3.75×10⁻⁵ Ω cm² (p‑type). A thick Al overlayer and polyimide encapsulation protect the front side during high‑voltage testing. SiC‑MOS capacitors, fabricated on an n‑type (7×10¹⁵ cm⁻³) epitaxial layer, provide a platform for DLTS analysis.

Diodes and MOS capacitors were irradiated for 72 h at 184.9 nm (mercury lamp) in air, with no bias applied. Post‑irradiation electrical measurements employed a Wentworth probe and Agilent B1505A system. DLTS characterization used a PhysTech FT‑DLTS system with reverse bias V_R = 15 V, pulse voltage V_P = 2 V, and 1.5 s pulse width.

Schematic cross‑section of the 4H‑SiC PiN diode

Results and Discussion

Figures 2 and 3 compare pre‑ and post‑UV characteristics for devices D1 and D2 (3.5 mm diameter, ~10 mm² active area). Forward voltage drops are virtually unchanged (≈3.95 V at 100 A/cm²), confirming that UV exposure does not affect conduction paths. In contrast, the blocking voltage of D1 rises from 7.0 kV to 9.2 kV (Δ = 2.2 kV), and D2 improves by 1.7 kV, approaching the theoretical 9.7 kV for a 60 µm drift layer. The initial ~70 % of the ideal blocking voltage likely reflects sub‑optimal JTE implantation.

Forward on‑state characteristics before and after UV irradiation

Reverse characteristics before and after UV irradiation

Surface traps profoundly influence electric‑field distribution and thus reverse blocking. High‑energy UV (≥5 eV) can convert strained C–C bonds into electron traps, increasing negative interface charge and shifting flat‑band voltage positively [11,12]. DLTS spectra (Figure 6) reveal two electron traps at 210 K (P1) and 490 K (P2). The P2 trap amplitude grows markedly post‑irradiation, indicating a higher density of deep defects. The increased fixed charge density attracts positive drift‑layer carriers to the interface, expanding the depletion width and homogenizing the field (Figures 4–5).

Simulated breakdown voltage vs. JTE implant concentration for varying surface negative charges (no charge, 1×10¹¹, 5×10¹¹, 1×10¹², 5×10¹², 1×10¹³ cm⁻²)

Electric‑field distributions for surface charge densities of 1×10¹¹ and 5×10¹² cm⁻²: (a) depletion evolution; (b) field cut‑line below the JTE/n‑drift junction (implant = 6×10¹⁶ cm⁻³)

DLTS spectra of 4H‑SiC MOS capacitors before and after UV irradiation; inset: Dit vs. activation energy

Conclusions

UV irradiation at 184.9 nm selectively enhances the blocking voltage of 4H‑SiC PiN diodes without degrading forward conduction. The mechanism involves UV‑induced deep‑level defects at the SiO₂/SiC interface that accumulate negative charge, attracting drift‑layer carriers to the surface and extending the depletion region. This charge redistribution mitigates edge field crowding and aligns the device’s blocking voltage closer to the theoretical limit. These insights pave the way for controlled UV processing to optimize SiC power device performance.

Availability of data and materials

All data are available without restrictions.