Mastering Loop and Exit Constructs in VHDL: A Practical Guide

In the previous tutorial we covered timing delays with the wait for statement and explored process loops. Now we’ll focus on a core VHDL construct that lets you execute code once and then repeat a block until a specific condition is met: the loop statement.

While a process can run indefinitely, you often need a controlled loop that can be broken out of gracefully. The loop statement in VHDL is the simplest form of such a construct, and it terminates only when an exit is encountered.

Syntax of a simple loop

loop
    -- statements
end loop;

Each exit breaks out of the innermost loop it resides in, and it can appear in any loop type.

Exercise

This tutorial demonstrates how to build a basic loop and exit it after a single iteration.

Example Code

entity T03_LoopTb is
end entity;

architecture sim of T03_LoopTb is
begin
    process is
    begin
        report "Hello!";
        loop
            report "Peekaboo!";
            exit;  -- Break out after first iteration
        end loop;
        report "Goodbye!";
        wait;  -- Suspend the process indefinitely
    end process;
end architecture;

Simulation Output (ModelSim)

VSIM 2> run
# ** Note: Hello!
#    Time: 0 ns  Iteration: 0  Instance: /t03_looptb
# ** Note: Peekaboo!
#    Time: 0 ns  Iteration: 0  Instance: /t03_looptb
# ** Note: Goodbye!
#    Time: 0 ns  Iteration: 0  Instance: /t03_looptb

The console shows that all messages occur at time 0 ns, confirming that statements other than wait consume no simulation time. The exit statement stops the loop after one iteration, after which the process hits the final wait and remains idle.

Analysis

By inspecting the timestamps, you can see the precise order of execution: report "Hello!" → report "Peekaboo!" → exit → report "Goodbye!". This example demonstrates how to use loop and exit to control flow without relying on complex state machines.

Key Takeaways

• loop creates an infinite loop that runs until exit is invoked.
• exit immediately terminates the current loop, regardless of nesting level.

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