Mastering For‑Loops in VHDL: A Practical Guide

In the previous tutorial we explored how to create an infinite loop using the loop statement and exit it with exit. What if we need the loop to run a specific number of times? The For‑Loop is the most straightforward solution.

A For‑Loop iterates over a fixed range of integers or enumerated items. The current iteration value is automatically available inside the loop through an implicitly declared constant.

This article is part of the Basic VHDL Tutorials series.

Syntax

for <constant> in <range> loop
    -- loop body
end loop;

Here, <constant> is a user‑defined name for the loop counter, and <range> can be an integer range (ascending or descending) or a set of enumerated values.

Integer Ranges

• Ascending range: 0 to 9 – iterates 0,1,2,…,9.
• Descending range: 9 downto 0 – iterates 9,8,7,…,0.
• Single value: 0 to 0 – iterates only 0.
• Empty range: 0 to -1 – loop body never executes.

Example Code

entity T04_ForLoopTb is
end entity;

architecture sim of T04_ForLoopTb is
begin
    process is
    begin
        for i in 1 to 10 loop
            report "i=" & integer'image(i);
        end loop;
        wait;
    end process;
end architecture;

Simulation Output (ModelSim)

VSIM 2> run
# ** Note: i=1
#    Time: 0 ns  Iteration: 0  Instance: /t04_forlooptb
# ** Note: i=2
#    Time: 0 ns  Iteration: 0  Instance: /t04_forlooptb
# ** Note: i=3
#    Time: 0 ns  Iteration: 0  Instance: /t04_forlooptb
# ** Note: i=4
#    Time: 0 ns  Iteration: 0  Instance: /t04_forlooptb
# ** Note: i=5
#    Time: 0 ns  Iteration: 0  Instance: /t04_forlooptb
# ** Note: i=6
#    Time: 0 ns  Iteration: 0  Instance: /t04_forlooptb
# ** Note: i=7
#    Time: 0 ns  Iteration: 0  Instance: /t04_forlooptb
# ** Note: i=8
#    Time: 0 ns  Iteration: 0  Instance: /t04_forlooptb
# ** Note: i=9
#    Time: 0 ns  Iteration: 0  Instance: /t04_forlooptb
# ** Note: i=10
#    Time: 0 ns  Iteration: 0  Instance: /t04_forlooptb

Analysis

The For‑Loop executed exactly ten iterations, printing the counter value at simulation time 0. Because there is no wait inside the loop, the entire loop completes instantly. The final wait; places the process in an infinite pause, which is common in testbenches.

We also demonstrated two essential string operations:

• integer'image(i) – converts an integer to a string.
• & – concatenates two strings.

Key Takeaways

• For‑Loops can iterate over both ascending (to) and descending (downto) ranges.
• Integer values are converted to strings with integer'image().
• String concatenation uses the & operator.

Proceed to the next tutorial for deeper VHDL concepts.