Mastering std_logic_vector: Creating Signal Vectors in VHDL

The std_logic_vector type is VHDL's standard for defining signal buses. While std_logic models a single wire’s state, std_logic_vector extends that to an array of wires, enabling the representation of multi‑bit buses.

Unlike the single‑bit std_logic, std_logic_vector is a composite type—an indexed collection of std_logic elements. It can hold an arbitrary number of bits, making it ideal for connecting components that exchange multi‑bit data.

This blog post is part of the Basic VHDL Tutorials series.

Declare a std_logic_vector signal with the following syntax:
signal <name> : std_logic_vector(<lsb> to <msb>) := <initial_value>;
or
signal <name> : std_logic_vector(<msb> downto <lsb>) := <initial_value>;
where <name> is a user‑chosen identifier and <initial_value> is optional. <lsb> and <msb> denote the least and most significant bit indices, respectively.

The to or downto keyword specifies the direction of the range (i.e., endianness). Both forms work, but most designers favor downto for clarity. I recommend consistently using downto when declaring bit vectors to avoid confusion.

The VHDL code for a byte‑sized vector is:

signal MySlv : std_logic_vector(7 downto 0);

The VHDL code for a one‑bit vector is:

signal MySlv : std_logic_vector(0 downto 0);

The VHDL code for an empty range (zero bits) is:

signal MySlv : std_logic_vector(-1 downto 0);

Exercise

In this video tutorial we will learn how to declare std_logic_vector signals and give them initial values. We also learn how to iterate over the bits in a vector using a For‑Loop to create a shift register:

The final code we created in this tutorial:

library ieee;
use ieee.std_logic_1164.all;

entity T11_StdLogicVectorTb is
end entity;

architecture sim of T11_StdLogicVectorTb is

    signal Slv1 : std_logic_vector(7 downto 0);
    signal Slv2 : std_logic_vector(7 downto 0) := (others => '0');
    signal Slv3 : std_logic_vector(7 downto 0) := (others => '1');
    signal Slv4 : std_logic_vector(7 downto 0) := x"AA";
    signal Slv5 : std_logic_vector(0 to 7)     := "10101010";
    signal Slv6 : std_logic_vector(7 downto 0) := "00000001";

begin

    -- Shift register
    process is
    begin

        wait for 10 ns;

        for i in Slv6'left downto Slv6'right + 1 loop
            Slv6(i) <= Slv6(i-1);
        end loop;

        Slv6(Slv6'right) <= Slv6(Slv6'left);

    end process;

end architecture;

The waveform window in ModelSim after we pressed run, and zoomed in on the timeline:

Analysis

In this exercise we declared six std_logic_vector buses, each eight bits long (one byte).

Signal Slv1 was declared without an initial value. The bus appears as XX in the waveform screenshot because the hexadecimal display cannot represent unknown values. A closer look reveals that the individual bits are actually U.

Signal Slv2 uses the aggregate assignment (others => '0') to set all bits to zero. This concise syntax ensures every element receives the specified value regardless of vector width.

Signal Slv3 employs the same aggregate technique to initialize every bit to one, which is displayed as FF (hex for eight 1s).

Signal Slv4 demonstrates a hexadecimal initializer: AA. Since each hex digit maps to four bits, two digits cover the 8‑bit vector.

Signal Slv5 contains the identical value, but expressed in binary (10101010). Both Slv4 and Slv5 render as AA in the waveform.

Signal Slv6 starts with all zeros except the least significant bit set to 1. A process implements a left‑shifting register that cycles the 1 through the vector every 10 ns.

The process leverages the left and right attributes to keep the code generic; resizing the vector does not require code changes.

Additional attributes exist, but they are beyond the scope of this introductory tutorial.

Takeaway

• N‑bit vectors should be declared using std_logic_vector(N-1 downto 0).
• A vector can be assigned as a whole or individual bits can be accessed.
• All bits can be zeroed with the aggregate assignment (others => '0').
• Using attributes like 'left and 'right makes code generic and maintainable.

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