Using Sensitivity Lists in VHDL Processes for Reliable RTL Design

In production-level VHDL, processes are typically driven by a sensitivity list rather than wait statements. A sensitivity list enumerates every signal that should wake the process when it changes.

While wait on and wait until are convenient for simulation, they are rarely used in synthesizable RTL. In synthesis, a wait statement is often ignored, leading to unpredictable hardware. Conversely, a sensitivity list maps directly to a combinational or clock‑synchronous block that synthesis tools can implement reliably.

Basic VHDL Tutorials – Process Sensitivity

When writing code for a simulator, I always rely on wait statements to control timing. For any design that will be synthesized into silicon, I avoid wait entirely and use sensitivity lists.

The syntax for a process with a sensitivity list is:

process( signal1, signal2, ... ) is
begin
    -- main logic here
end process;

Note that every signal read inside the process must appear in the list. The VHDL compiler does not flag a missing signal, but omitting one will change the behavior after synthesis.

VHDL‑2008 introduced the keyword all to automatically include every read signal, e.g. process(all). However, most commercial synthesizers still lack support for this feature.

Exercise

In the accompanying video tutorial, we walk through building a process that uses a sensitivity list.

The final VHDL snippet produced in this lesson is:

entity T09_SensitivityListTb is
end entity;

architecture sim of T09_SensitivityListTb is

    signal CountUp   : integer := 0;
    signal CountDown : integer := 10;

begin

    process is
    begin
        CountUp   <= CountUp + 1;
        CountDown <= CountDown - 1;
        wait for 10 ns;
    end process;

    -- Process triggered using Wait On
    process is
    begin
        if CountUp = CountDown then
            report "Process A: Jackpot!";
        end if;
        wait on CountUp, CountDown;
    end process;

    -- Equivalent process using a sensitivity list
    process(CountUp, CountDown) is
    begin
        if CountUp = CountDown then
            report "Process B: Jackpot!";
        end if;
    end process;

end architecture;

Running this testbench in ModelSim yields:

VSIM 2> run
# ** Note: Process A: Jackpot!
#    Time: 40 ns  Iteration: 1  Instance: /t09_sensitivitylisttb
# ** Note: Process B: Jackpot!
#    Time: 40 ns  Iteration: 1  Instance: /t09_sensitivitylisttb

Analysis

The console output demonstrates that both the wait on process and the sensitivity‑list process fire under identical conditions. This equivalence holds because a sensitivity list implicitly behaves like a wait on placed at the end of the process.

In practice, sensitivity lists are the de‑facto standard for synthesizable RTL. They provide clear intent, allow synthesis tools to generate correct hardware, and avoid the ambiguities that wait statements can introduce.

Key Takeaways

• A sensitivity‑list process is functionally identical to a process ending with wait on.
• All signals read inside the process must appear on its sensitivity list.
• Use wait statements for simulation-only code; use sensitivity lists for synthesizable RTL.

Proceed to the next tutorial here.