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Mastering Conditional Logic in VHDL: If-Then-Elsif-Else Explained

In the previous tutorial we used a conditional expression with the Wait Until statement to trigger a process only when two counter signals matched. What if we need the program to take different actions based on varying inputs?

The If-Then-Elsif-Else construct lets us branch our logic. Depending on a variable’s value or the result of an expression, the program can follow distinct paths.

This article is part of the Basic VHDL Tutorials series.

Basic Syntax

The canonical form is:

if <condition> then
elsif <condition> then
else
end if;

The elsif and else clauses are optional, and elsif can appear multiple times. A <condition> may be a boolean literal or an expression that evaluates to true or false.

Example: MyCounter < 10 is true when MyCounter is less than ten.

Relational Operators

=equal
/=not equal
<less than
<=less than or equal
>greater than
>=greater than or equal

Logical Operators

not atrue if a is false
a and btrue if a and b are true
a or btrue if a or b are true
a nand btrue if a or b is false
a nor btrue if a and b are false
a xor btrue if exactly one of a or b are true
a xnor btrue if a and b are equal

Exercise

Below is a complete VHDL example that demonstrates the If-Then-Elsif-Else construct in action.

Final code:

entity T08_IfTb is
end entity;

architecture sim of T08_IfTb is

    signal CountUp   : integer := 0;
    signal CountDown : integer := 10;

begin

    process is
    begin

        CountUp   <= CountUp + 1;
        CountDown <= CountDown - 1;
        wait for 10 ns;

    end process;

    process is
    begin

        if CountUp > CountDown then
            report "CountUp is larger";
        elsif CountUp < CountDown then
            report "CountDown is larger";
        else
            report "They are equal";
        end if;

        wait on CountUp, CountDown;

    end process;

end architecture;

Simulator console output when running the model in ModelSim:

VSIM 2> run
# ** Note: CountDown is larger
#    Time: 0 ns  Iteration: 0  Instance: /t08_iftb
# ** Note: CountDown is larger
#    Time: 0 ns  Iteration: 1  Instance: /t08_iftb
# ** Note: CountDown is larger
#    Time: 10 ns  Iteration: 1  Instance: /t08_iftb
# ** Note: CountDown is larger
#    Time: 20 ns  Iteration: 1  Instance: /t08_iftb
# ** Note: CountDown is larger
#    Time: 30 ns  Iteration: 1  Instance: /t08_iftb
# ** Note: They are equal
#    Time: 40 ns  Iteration: 1  Instance: /t08_iftb
# ** Note: Countup is larger
#    Time: 50 ns  Iteration: 1  Instance: /t08_iftb
# ** Note: Countup is larger
#    Time: 60 ns  Iteration: 1  Instance: /t08_iftb
...

Analysis

We initialized CountDown to 10 and CountUp to 0. Both counters are updated simultaneously every 10 ns in the first process. The second process waits on these signals, so it triggers each time they change. The If-Then-Elsif-Else block then selects one of three branches: CountUp > CountDown, CountUp < CountDown, or CountUp = CountDown. Although an explicit else is not mandatory, including it is a best practice, ensuring all edge cases are handled.

The console trace confirms that the second process evaluates the condition after each update, printing the appropriate message.

Mastering Conditional Logic in VHDL: If-Then-Elsif-Else Explained

Takeaway

Continue to the next tutorial »

VHDL

  1. Leveraging In‑Process Procedures for Cleaner VHDL FSM Design
  2. Using Impure Functions in VHDL: Enhancing FSM Readability and Maintainability
  3. Mastering VHDL Functions: A Practical Guide to Efficient Design
  4. Using Procedures in VHDL: Simplify Your Design with Reusable Code
  5. Mastering the Case-When Statement in VHDL: Efficient Multiplexer Design
  6. Mastering Signed and Unsigned Types in VHDL: A Practical Guide
  7. Mastering VHDL Wait Statements: Wait On, Wait Until, and Combined Usage
  8. Mastering While Loops in VHDL: Dynamic Iteration Control
  9. Mastering For‑Loops in VHDL: A Practical Guide
  10. Mastering Loop and Exit Constructs in VHDL: A Practical Guide