Mastering VHDL Wait Statements: Wait On, Wait Until, and Combined Usage

In our previous tutorial we explored the differences between signals and variables in VHDL, emphasizing that signals have a broader scope than variables, which are confined to a single process. The next logical question is how to coordinate multiple processes using signals.

Beyond the familiar wait; (infinite pause) and wait for (time‑based pause), VHDL offers two powerful statements for event‑driven synchronization: Wait On and Wait Until. These can also be combined with wait for to create sophisticated control flows.

Wait On

The wait on statement suspends a process until any of the listed signals changes value.

wait on <signal_name1>, <signal_name2>, ...;

Wait Until

The wait until statement pauses execution until a specified Boolean condition becomes true.

wait until <condition>;

Combining Wait Statements

All three constructs can be used together to create nuanced timing behaviors:

wait on <signal_name1> until <condition> for <time_value>;

For example, the following line will pause for 10 ns or until signal1 changes and signal2 equals signal3:

wait on signal1 until signal2 = signal3 for 10 ns;

Practical Example

Below is a complete testbench that demonstrates how wait on and wait until can be used for inter‑process communication.

entity T07_WaitOnUntilTb is
end entity;

architecture sim of T07_WaitOnUntilTb is

    signal CountUp   : integer := 0;
    signal CountDown : integer := 10;

begin

    process is
    begin
        CountUp   <= CountUp + 1;
        CountDown <= CountDown - 1;
        wait for 10 ns;
    end process;

    process is
    begin
        wait on CountUp, CountDown;
        report "CountUp=" & integer'image(CountUp) &
            " CountDown=" & integer'image(CountDown);
    end process;

    process is
    begin
        wait until CountUp = CountDown;
        report "Jackpot!";
    end process;

end architecture;

The console output in ModelSim illustrates the sequence of events:

VSIM 2> run
# ** Note: CountUp=1 CountDown=9
#    Time: 0 ns  Iteration: 1  Instance: /t07_waitonuntiltb
# ** Note: CountUp=2 CountDown=8
#    Time: 10 ns  Iteration: 1  Instance: /t07_waitonuntiltb
# ** Note: CountUp=3 CountDown=7
#    Time: 20 ns  Iteration: 1  Instance: /t07_waitonuntiltb
# ** Note: CountUp=4 CountDown=6
#    Time: 30 ns  Iteration: 1  Instance: /t07_waitonuntiltb
# ** Note: CountUp=5 CountDown=5
#    Time: 40 ns  Iteration: 1  Instance: /t07_waitonuntiltb
# ** Note: Jackpot!
#    Time: 40 ns  Iteration: 1  Instance: /t07_waitonuntiltb
# ** Note: CountUp=6 CountDown=4
#    Time: 50 ns  Iteration: 1  Instance: /t07_waitonuntiltb
# ** Note: CountUp=7 CountDown=3
#    Time: 60 ns  Iteration: 1  Instance: /t07_waitonuntiltb
# ** Note: CountUp=8 CountDown=2
#    Time: 70 ns  Iteration: 1  Instance: /t07_waitonuntiltb
# ** Note: CountUp=9 CountDown=1
#    Time: 80 ns  Iteration: 1  Instance: /t07_waitonuntiltb
# ** Note: CountUp=10 CountDown=0
#    Time: 90 ns  Iteration: 1  Instance: /t07_waitonuntiltb
# ** Note: CountUp=11 CountDown=-1
#    Time: 100 ns  Iteration: 1  Instance: /t07_waitonuntiltb

Analysis

The first process updates CountUp and CountDown simultaneously every 10 ns. Because signal assignments only take effect after a wait statement, both counters are updated together at each simulation step.

The second process uses wait on CountUp, CountDown;, suspending until either counter changes. As shown, this triggers at 0 ns (the initial update) and subsequently whenever either signal changes.

The third process employs wait until CountUp = CountDown;. It awakens on every signal change but proceeds only when the equality holds. Consequently, the “Jackpot!” message appears only once—at 40 ns when both counters reach 5.

Takeaway

• Wait On pauses until any specified signal changes.
• Wait Until wakes on a signal change but continues only if a condition evaluates to true.
• All three constructs—wait on, wait until, and wait for—can be combined for granular control.

Proceed to the next tutorial for deeper insights into VHDL synchronization.