Understanding the Difference Between Signals and Variables in VHDL

In our previous tutorial we explored how to declare a variable within a process. Variables are ideal for local algorithmic work, but they cannot be seen outside that process. When you need a value to be shared with other parts of the design, you use a signal.

Signals are declared in the declarative region of an architecture – that is, between the line architecture <architecture_name> of <entity_name> is and the begin keyword.

This post is part of the Basic VHDL Tutorials series.

The syntax for declaring a signal is:
signal <name> : <type>;

A signal may optionally be declared with an initial value:
signal <name> : <type> := <initial_value>;

Exercise

In this video tutorial we learn how to declare a signal and discover the core difference between a variable and a signal.

The final code we created in this tutorial:

entity T06_SignalTb is
end entity;

architecture sim of T06_SignalTb is

    signal MySignal : integer := 0;

begin

    process is
        variable MyVariable : integer := 0;
    begin

        report "*** Process begin ***";

        MyVariable := MyVariable + 1;
        MySignal   <= MySignal + 1;

        report "MyVariable=" & integer'image(MyVariable) &
            ", MySignal=" & integer'image(MySignal);

        MyVariable := MyVariable + 1;
        MySignal   <= MySignal + 1;

        report "MyVariable=" & integer'image(MyVariable) &
            ", MySignal=" & integer'image(MySignal);

        wait for 10 ns;

        report "MyVariable=" & integer'image(MyVariable) &
            ", MySignal=" & integer'image(MySignal);

    end process;

end architecture;

The output to the simulator console when we pressed the run button in ModelSim:

VSIM 2> run
# ** Note: *** Process begin ***
#    Time: 0 ns  Iteration: 0  Instance: /t06_signaltb
# ** Note: MyVariable=1, MySignal=0
#    Time: 0 ns  Iteration: 0  Instance: /t06_signaltb
# ** Note: MyVariable=2, MySignal=0
#    Time: 0 ns  Iteration: 0  Instance: /t06_signaltb
# ** Note: MyVariable=2, MySignal=1
#    Time: 10 ns  Iteration: 0  Instance: /t06_signaltb
# ** Note: *** Process begin ***
#    Time: 10 ns  Iteration: 0  Instance: /t06_signaltb
# ** Note: MyVariable=3, MySignal=1
#    Time: 10 ns  Iteration: 0  Instance: /t06_signaltb
# ** Note: MyVariable=4, MySignal=1
#    Time: 10 ns  Iteration: 0  Instance: /t06_signaltb
# ** Note: MyVariable=4, MySignal=2
#    Time: 20 ns  Iteration: 0  Instance: /t06_signaltb
...

Analysis

We created a signal and a variable with the same initial value of 0. Although we treated them identically in the process, the console output reveals distinct behaviours. The key differences are:

• Variables use the := operator and are updated immediately within the process.
• Signals use the <= operator; the new value is scheduled and only takes effect when the process suspends (e.g., at a wait statement).
• When a signal is assigned multiple times before the process resumes, only the last assignment “wins” because earlier scheduled values are overwritten.

In our example, the first two increments of MySignal were lost because they were overwritten before the wait for 10 ns; statement caused the process to suspend and the signal to update. The subsequent increment appears after the suspension, matching the expected behaviour.

Takeaway

• Use variables for temporary values that need immediate, local updates.
• Use signals when you need to communicate changes to other processes or components.
• Remember that signal assignments are scheduled and only committed when the process pauses; multiple assignments without a pause will result in only the last value surviving.

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