Using Wait-For Statements to Delay Execution in VHDL
In our previous tutorial we compared a VHDL process to a program thread and introduced the wait; statement, which suspends a process indefinitely. But what if you need a process to pause for a specific duration?
Removing the wait; entirely triggers a compiler error because every VHDL process is an infinite loop that must contain at least one wait statement. The loop runs continuously between the begin and end process; delimiters.
This article is part of the Basic VHDL Tutorials series.
While wait; halts execution forever, the wait for construct allows you to delay a process for any desired time interval.
The syntax of wait for is:
wait for <time_value> <time_unit>;
where <time_value> is a numeric literal and <time_unit> can be one of the following:
| fs | femtoseconds |
| ps | picoseconds |
| ns | nanoseconds |
| us | microseconds |
| ms | milliseconds |
| sec | seconds |
| min | minutes |
| hr | hours |
Exercise
Watch the tutorial video to see wait for in action, pausing a process for a user‑defined period.
The example VHDL we constructed is shown below:
entity T02_WaitForTb is
end entity;
architecture sim of T02_WaitForTb is
begin
process is
begin
-- Process "thread" starts here
report "Peekaboo!";
wait for 10 ns;
-- Loop back to the start
end process;
end architecture;
Running this in ModelSim produces the following console output:
VSIM 2> run # ** Note: Peekaboo! # Time: 0 ns Iteration: 0 Instance: /t02_waitfortb # ** Note: Peekaboo! # Time: 10 ns Iteration: 0 Instance: /t02_waitfortb # ** Note: Peekaboo! # Time: 20 ns Iteration: 0 Instance: /t02_waitfortb ...
Analysis
In this example the 10 ns delay is typical for logic operating at MHz frequencies, where nanosecond granularity aligns with clock periods.
During simulation, the report statement and loop control consume zero time; only the wait for statement advances simulation time.

Takeaway
- A VHDL process pauses precisely for the duration specified in
wait for. - All other statements in a process execute instantaneously in simulation time.
Proceed to the next tutorial →
VHDL
- Creating a Tcl-Driven Testbench for a VHDL Code‑Lock Module
- Leveraging In‑Process Procedures for Cleaner VHDL FSM Design
- Mastering VHDL Functions: A Practical Guide to Efficient Design
- Building a Clock‑Triggered Process in VHDL: A Practical Guide
- Mastering Concurrent Statements in VHDL: A Practical Guide
- Using Sensitivity Lists in VHDL Processes for Reliable RTL Design
- Mastering VHDL Wait Statements: Wait On, Wait Until, and Combined Usage
- Your First VHDL Program: A Step‑by‑Step Hello World Tutorial
- Free VHDL Simulator & Editor Setup: A Student’s Guide
- Accelerate Robot Welding Training: Cut Time, Boost Efficiency