Microchip Launches Defense‑Grade PolarFire SoC FPGA with Early Access Program

Microchip Technology introduces the PolarFire SoC FPGA, a defense‑grade platform that combines a hardened RISC‑V CPU cluster with FPGA fabric, enabling secure, real‑time Linux applications at the edge. The early‑access program (EAP) invites qualified developers to begin design work immediately.

The chip is the first industry‑first SoC FPGA featuring a deterministic, coherent RISC‑V CPU cluster and a dedicated 2 MB L2 memory subsystem. This architecture supports Linux alongside deterministic real‑time workloads, offering a single‑chip solution that balances performance, security, and power efficiency.

Its 2 MB L2 memory can be configured as a cache, scratchpad, or direct‑access memory, giving embedded designers flexibility while retaining the deterministic nature required for safety‑critical applications.

PolarFire SoC incorporates a suite of defense‑grade features: SEC‑DED protection on all memories, physical memory protection, a DPA‑resistant crypto core, secure boot, and 128 Kb of flash boot memory—all designed to meet the most stringent security standards.

“RISC‑V enabled us to combine Linux with real‑time performance on a single processor,” said Ted Speers, technical fellow and head of product architecture at Microchip. “With the low‑power, reliable PolarFire foundation, we delivered a unified platform that meets both operating system and hard‑real‑time requirements.”

Embedding FPGA fabric and a CPU on one die is increasingly attractive to embedded designers. The approach reduces component count, lowers power consumption, shrinks board area, and improves task‑specific processing with minimal latency.

PolarFire SoC delivers up to 50 % lower power consumption than comparable devices, eliminating the need for fans and heat sinks in small‑form‑factor systems and easing thermal management constraints.

“Our technology consistently achieves 50 % lower power than competing FPGAs,” Speers noted. “In compact environments where heat removal is critical, the ability to eliminate fans translates to cost savings and simplified system design.”

Customers who previously used Microchip’s SmartFusion 2— the industry’s first SoC FPGA with a full processor subsystem—can transition smoothly to PolarFire SoC. Shared peripherals, firmware drivers, and the same development tools ensure a straightforward upgrade path.

The PolarFire SoC excels in thermally‑challenged industrial IoT switches, remote radio heads, battery‑powered portable thermal imagers, ultrasound devices, secure military radios, portable test and measurement, machine learning, and root‑of‑trust applications—supporting weapons platforms, UAVs, and more.

Microchip’s expanding RISC‑V ecosystem includes partners such as WindRiver, Mentor Graphics, WolfSSL, ExpressLogic, Veridify, Hex‑Five, FreeRTOS, and tool vendors IAR Systems and AdaCore.

Early‑Access Program members can start designing right away with Microchip’s Libero SoC 12.3 FPGA design suite and SoftConsole 6.2 IDE. Embedded applications can be debugged in Renode, a virtual model of the processor subsystem.

PolarFire SoC debugging features encompass instruction trace, passive AXI bus monitors from Mi‑V partner UltraSoC, 50 breakpoints, FPGA fabric monitors, and Microchip’s built‑in SmartDebug two‑channel logic analyzer.

To join the EAP, contact PolarFireSoC@microchip.com. Qualified customers receive schematic and Gerber files for the PolarFire Icicle Kit—available in Q3 2020—as well as board design guidelines. The MPFS250T will enter production in Q3 2020.