Innatera Unveils First Neuromorphic AI Chips for Ultra‑Low‑Power Edge Applications

Innatera, a Dutch startup specializing in neuromorphic AI accelerators for spiking neural networks (SNNs), has produced its first chips, benchmarked their performance, and revealed key architectural details.

The company also announced that Alberto Sangiovanni‑Vincentelli—co‑founder of Cadence and Synopsys—has joined as chairman of the board. Sangiovanni‑Vincentelli is currently a professor at UC Berkeley and brings decades of industry experience.

Innatera’s chip is designed to accelerate different SNNs for audio, health and radar applications (Image: Innatera)

Unlike conventional AI models, SNNs mimic the brain’s spiking activity, using the precise timing of electrical pulses to perform pattern recognition. Because of this unique computational paradigm, SNNs demand dedicated hardware that can process time‑series data efficiently while consuming minimal power.

While many rivals such as Prophesee target image and video streams, Innatera focuses on audio (speech recognition), health (vital‑sign monitoring), and radar (privacy‑preserving fall detection for the elderly). These domains rely on continuous time‑series data and require tight power envelopes at the sensor node.

Marco Jacobs (Image: Innatera)

“Our array excels at processing time‑series data, which is the core of audio, health, and radar applications,” said Marco Jacobs, VP of Marketing and Business Development. “There are few solutions that address these needs effectively.”

Innatera’s tests show each spike event consumes less than a picojoule—under 200 fJ in a TSMC 28 nm process—approaching the energy used by biological neurons. A typical keyword‑spotting task required fewer than 500 spikes per inference, yielding sub‑milliwatt power dissipation, according to CEO Sumeet Kumar.

Clusters of neurons firing (groups of dots) represent detection of phonemes in speech. As input data incorporates more noise, the same clusters are mostly present, though they are harder to spot (Image: Innatera)

Processing Architecture

Innatera’s processor uses a massively parallel neuro‑synaptic array with spike encoders and decoders, operating in an analog/mixed‑signal domain to preserve continuous‑time dynamics.

Innatera’s spiking neural processor includes a massively parallel neuro‑synaptic array and spike encoders and decoders (Image: Innatera)

The architecture emphasizes programmability, enabling flexible neuron connectivity and fine‑grained spike‑timing adjustments via the SDK. This flexibility is essential for reproducing the brain’s complex network topologies in silicon and for optimizing performance on diverse SNN workloads.

Neurons and synapses are implemented in analog silicon to maintain ultra‑low power and to allow continuous‑time state retention—tasks that would be costly to discretize in pure digital circuits. “Analog domains naturally preserve state information, eliminating the need to encode it into network topology,” said Kumar.

A compute segment in Innatera’s array, where the neurons are designed to be carefully matched. Programmable synapses are arranged in a multi‑level crossbar structure. (Black lines/dashes here represent input and output spikes) (Image: Innatera)

To mitigate fabrication variability, Innatera groups neurons into tightly matched segments, ensuring deterministic behavior across the array. Software in the SDK compensates for residual mismatches, allowing developers to focus on application logic rather than low‑level calibration.

Application‑Specific Focus

Spun out from Delft University of Technology, Innatera secured €5 million (≈$6 million) in seed funding by the end of 2020. The company has already engaged with revenue customers, delivering mature SNN algorithms before transitioning to hardware.

“We are a compute‑solutions company,” said Kumar. “We provide turnkey solutions that combine hardware with application‑specific SNN algorithms.”

The first chip is validated for audio, health, and radar use cases, with a roadmap that may introduce further optimizations tailored to each domain. “Our architecture supports a broad range of SNNs across applications, but we will continue to refine the hardware for deeper domain integration,” added Kumar.

Initial chip samples are expected to ship before the end of 2021.

> This article was originally published on our sister site, EE Times.

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