IBM Master Inventor Lukas Czornomaz: From an 8‑Year‑Old Circuit Builder to Pioneering Hybrid CMOS Technology

National Inventors’ Day honors the brilliance of inventors worldwide. At IBM Research Zurich, we sat down with Master Inventor Lukas Czornomaz to discuss his career and the patents that define his impact.

Lukas Czornomaz and Veeresh Deshpande take home the Best Student Paper Award of the IEEE 2016 Symposium on VLSI Technology

Lukas Czornomaz specializes in semiconductor technology and leads research projects in Advanced CMOS, Photonics, and RF/mm‑Wave for the Internet‑of‑Things. He recently earned the Best Student Paper Award at the IEEE 2016 Symposium on VLSI Technology and the 2017 Compound Semiconductor Industry Innovation Award for the first InGaAs/SiGe CMOS circuits on silicon substrates using 300 mm‑wafer processes compatible with high‑volume manufacturing. His portfolio now includes up to 35 patents across CMOS, photonics, non‑volatile memories, neuromorphic computing, and sensors.

Could you give us a simple explanation of the technology you’re developing?

Lukas Czornomaz (LC): I work on CPUs—the central processing units that act as the brain of a computer. CPUs comprise billions of transistors that switch on and off, and their performance hinges on the number and speed of these switches. Power efficiency is equally critical; excessive power can damage the chip.

When it comes to size, do smaller transistors perform better?

LC: For decades, shrinking transistors was the primary path to faster, denser, and more power‑efficient CPUs. However, silicon scaling has hit fundamental limits: smaller transistors no longer guarantee faster switching or better power efficiency without trade‑offs. We now need to rethink how we achieve performance gains.

Your work aims to break away from pure silicon to address the scaling problem.

LC: Exactly. Our team is exploring III‑V semiconductors—elements from columns III and V of the periodic table. These materials offer superior charge‑carrier mobility, enabling electrons to travel at much higher velocities than in silicon. This can halve the operating voltage, reducing power consumption by a factor of four while maintaining performance.

What have you discovered so far?

LC: Over five years, we demonstrated that hybrid integration of InGaAs/SiGe is a viable path to improve the power‑performance ratio beyond the 7 nm node. We combined selective growth of high‑quality InGaAs on silicon, fabrication of InGaAs and SiGe FinFETs, and the processing of functional 6T‑SRAM cells—all on a single platform.

But what does it all mean? Are there any real advantages to this hybrid technology?

LC: We anticipate at least a 25 % performance boost at the same power, or a 50 % power reduction at the same performance. In practical terms, that could double battery life for mobile devices and unlock new possibilities for advanced CMOS in IoT, RF, and integrated photonics.

How many patents came out of this research project? Is there one that stands out?

LC: About 15 patents were granted during the project. The most significant is US 9,640,394, which protects our selective‑epitaxy integration method using empty oxide cavities—a real paradigm shift for co‑integrating disparate semiconductors on silicon.

What’s next?

LC: Although we’ve proven the hybrid solution’s scalability, we must ensure the compound materials maintain quality in mass production. Future work will focus on making the technology manufacturable and exploring RF communication and integrated photonic devices for IoT.

Tell us something about yourself that very few people know.

(LC): I built my first electronic circuit at eight, and after 20 years I designed an integrated circuit on silicon from the ground up using the most advanced available technology.

Lukas Czornomaz and two other IBM Master Inventors discuss the meaning of the role: