VHDL Procedure Example: Incrementing a Standard Logic Vector
What Is a VHDL Procedure?
\nProcedures belong to the subprogram family in VHDL. They encapsulate reusable logic, reducing code duplication and improving maintainability. By defining a procedure once, you can invoke it from multiple processes or architectures, ensuring consistent behavior.
\nExample: Incrementing a std_logic_vector
\nThe following example demonstrates a procedure that takes an 8‑bit std_logic_vector, adds one to it, and returns the result. The procedure also includes a 1‑ns wait to illustrate timing control within a testbench.
\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity example_procedure_simple is\nend example_procedure_simple;\n\narchitecture behave of ex_procedure_simple is\n\n signal r_TEST : std_logic_vector(7 downto 0) := X\"42\";\n\n -- Purpose: Increments a std_logic_vector by 1\n procedure p_INCREMENT_SLV (\n signal r_IN : in std_logic_vector(7 downto 0);\n signal r_OUT : out std_logic_vector(7 downto 0)\n ) is\n begin\n r_OUT <= std_logic_vector(unsigned(r_IN) + 1);\n wait for 1 ns; -- Wait is OK here.\n end p_INCREMENT_SLV;\n\n\nbegin\n\n process is\n begin\n wait for 10 ns;\n p_INCREMENT_SLV(r_TEST, r_TEST);\n wait for 10 ns;\n p_INCREMENT_SLV(r_TEST, r_TEST);\n wait for 10 ns;\n p_INCREMENT_SLV(r_TEST, r_TEST);\n wait;\n end process; \n \nend behave;\n\n
Why Include a Wait Statement?
\nWait statements are legal inside a procedure provided the calling process has no sensitivity list. This feature is especially useful in testbenches, where you may need to introduce deterministic delays without cluttering the main process.
\nKey Takeaways
\n- \n
- Procedures can have both IN and OUT signals. \n
- They are ideal for common operations like arithmetic on std_logic_vector. \n
- Using wait inside a procedure keeps testbench logic tidy. \n
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