Leveraging VHDL Records for Clean, Reusable FIFO Interfaces

In VHDL, records offer a powerful way to streamline your design, much like structs in C. By grouping related signals into a single type, you can dramatically reduce code duplication, improve readability, and simplify port maps across multiple entities.

Records shine when you work with large, recurring interfaces—such as those connecting to off‑chip memories or FIFOs—where the same set of control and data signals appears repeatedly. Defining a record once in a package and reusing it everywhere keeps your entity interfaces tidy and eases future modifications.

The following example demonstrates how to create two record types in a dedicated package (example_record_pkg.vhd) and use them to model a FIFO’s input and output signals. A single record signal represents all inputs from the FIFO, and another represents all outputs to the FIFO.

Key takeaways:

1. Records simplify entity declarations and port maps in VHDL.
2. They can hold elements of varying types—std_logic, integer, std_logic_vector, etc.
3. Records are analogous to C structs, providing a familiar paradigm for many engineers.
4. Shared record types should reside in a single package for consistency.
5. Record signals can be initialized with constants for predictable start‑up values.
6. Arrays of records enable structured data handling, such as a table of FIFO configurations.

Below is the package definition, followed by an example entity that uses the record types to manage FIFO read/write logic. The code is fully compliant with the IEEE 1076‑2008 standard.

library ieee;
use ieee.std_logic_1164.all;

package example_record_pkg is

  -- Outputs from the FIFO.
  type t_FROM_FIFO is record
    wr_full  : std_logic;                -- FIFO Full Flag
    rd_empty : std_logic;                -- FIFO Empty Flag
    rd_dv    : std_logic;
    rd_data  : std_logic_vector(7 downto 0);
  end record t_FROM_FIFO;  

  -- Inputs to the FIFO.
  type t_TO_FIFO is record
    wr_en    : std_logic;
    wr_data  : std_logic_vector(7 downto 0);
    rd_en    : std_logic;
  end record t_TO_FIFO;

  constant c_FROM_FIFO_INIT : t_FROM_FIFO := (wr_full => '0',
                                              rd_empty => '1',
                                              rd_dv => '0',
                                              rd_data => (others => '0'));

  constant c_TO_FIFO_INIT : t_TO_FIFO := (wr_en => '0',
                                          wr_data => (others => '0'),
                                          rd_en => '0');
  
end package example_record_pkg;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.example_record_pkg.all; -- USING PACKAGE HERE!

entity example_record is
  port (
    i_clk  : in  std_logic;
    i_fifo : in  t_FROM_FIFO;
    o_fifo : out t_TO_FIFO := c_TO_FIFO_INIT  -- intialize output record
    );
end example_record;

architecture behave of example_record is

  signal r_WR_DATA : unsigned(7 downto 0) := (others => '0');
  
begin

  -- Handles writes to the FIFO
  p_FIFO_WR : process (i_clk) is
  begin 
    if rising_edge(i_clk) then
      if i_fifo.wr_full = '0' then
        o_fifo.wr_en   <= '1';
        o_fifo.wr_data <= std_logic_vector(r_WR_DATA + 1);
      end if;
    end if;
  end process p_FIFO_WR;
  
  -- Handles reads from the FIFO
  p_FIFO_RD : process (i_clk) is
  begin 
    if rising_edge(i_clk) then
      if i_fifo.rd_empty = '0' then
        o_fifo.rd_en <= '1';
      end if;
    end if;
  end process p_FIFO_RD;
  
end behave;