Comprehensive Guide to VHDL Type Conversions with Numeric_Std and Std_Logic_Arith

Using both Numeric_Std and Std_Logic_Arith Package Files

Below you’ll find the most frequently used VHDL type conversions. The article is divided into two sections: the first showcases conversions that rely on the modern numeric_std package, while the second demonstrates equivalent conversions using the legacy std_logic_arith package. While many designers still employ std_logic_arith, industry best practice recommends numeric_std for its clarity and portability.

Notice that many examples employ the VHDL attribute 'length, which ensures your code adapts automatically to vector width changes – a key strategy for reusable, maintainable designs.

Example Conversions using Numeric Std

Integer to Signed
Integer to Std_Logic_Vector
Integer to Unsigned
Std_Logic_Vector to Integer
Std_Logic_Vector to Signed
Std_Logic_Vector to Unsigned
Signed to Integer
Signed to Std_Logic_Vector
Signed to Unsigned
Unsigned to Integer
Unsigned to Signed
Unsigned to Std_Logic_Vector

Example Conversions using Std_Logic_Arith

Integer to Signed
Integer to Std_Logic_Vector
Integer to Unsigned
Std_Logic_Vector to Integer
Std_Logic_Vector to SignedStd_Logic_Vector to Unsigned
Signed to Integer
Signed to Std_Logic_Vector
Signed to Unsigned
Unsigned to Integer
Unsigned to Signed
Unsigned to Std_Logic_Vector

Convert from Integer to Signed using Numeric_Std

The to_signed function requires two arguments: the integer to convert and the desired vector width. Using the 'length attribute keeps the code flexible.

signal input_3  : integer;
signal output_3 : signed(3 downto 0);

output_3 <= to_signed(input_3, output_3'length);

Convert from Integer to Std_Logic_Vector using Numeric_Std

Determine whether the integer range is signed or unsigned. For positive‑only values use to_unsigned; for signed values use to_signed. Both functions accept the value and the target width.

signal input_1   : integer;
signal output_1a : std_logic_vector(3 downto 0);
signal output_1b : std_logic_vector(3 downto 0);

-- Positive integers only
output_1a <= std_logic_vector(to_unsigned(input_1, output_1a'length));

-- Signed or unsigned integers
output_1b <= std_logic_vector(to_signed(input_1, output_1b'length));

Convert from Integer to Unsigned using Numeric_Std

signal input_2  : integer;
signal output_2 : unsigned(3 downto 0);

output_2 <= to_unsigned(input_2, output_2'length);

Convert from Std_Logic_Vector to Integer using Numeric_Std

First cast the vector to unsigned or signed depending on the data semantics, then apply to_integer.

signal input_4   : std_logic_vector(3 downto 0);
signal output_4a : integer;
signal output_4b : integer;

-- Unsigned case
output_4a <= to_integer(unsigned(input_4));

-- Signed case
output_4b <= to_integer(signed(input_4));

Convert from Std_Logic_Vector to Signed using Numeric_Std

signal input_6  : std_logic_vector(3 downto 0);
signal output_6 : signed(3 downto 0);

output_6 <= signed(input_6);

Convert from Std_Logic_Vector to Unsigned using Numeric_Std

signal input_5  : std_logic_vector(3 downto 0);
signal output_5 : unsigned(3 downto 0);

output_5 <= unsigned(input_5);

Convert from Signed to Integer using Numeric_Std

signal input_10  : signed(3 downto 0);
signal output_10 : integer;

output_10 <= to_integer(input_10);

Convert from Signed to Std_Logic_Vector using Numeric_Std

signal input_11  : signed(3 downto 0);
signal output_11 : std_logic_vector(3 downto 0);

output_11 <= std_logic_vector(input_11);

Convert from Signed to Unsigned using Numeric_Std

signal input_12  : signed(3 downto 0);
signal output_12 : unsigned(3 downto 0);

output_12 <= unsigned(input_12);

Convert from Unsigned to Integer using Numeric_Std

signal input_7  : unsigned(3 downto 0);
signal output_7 : integer;

output_7 <= to_integer(input_7);

Convert from Unsigned to Signed using Numeric_Std

signal input_9  : unsigned(3 downto 0);
signal output_9 : signed(3 downto 0);

output_9 <= signed(input_9);

Convert from Unsigned to Std_Logic_Vector using Numeric_Std

signal input_8  : unsigned(3 downto 0);
signal output_8 : std_logic_vector(3 downto 0);

output_8 <= std_logic_vector(input_8);

Convert from Integer to Signed using Std_Logic_Arith

signal input_3  : integer;
signal output_3 : signed(3 downto 0);

output_3 <= conv_signed(input_3, output_3'length);

Convert from Integer to Std_Logic_Vector using Std_Logic_Arith

signal input_1  : integer;
signal output_1 : std_logic_vector(3 downto 0);

output_1 <= conv_std_logic_vector(input_1, output_1'length);

Convert from Integer to Unsigned using Std_Logic_Arith

signal input_2  : integer;
signal output_2 : unsigned(3 downto 0);

output_2 <= conv_unsigned(input_2, output_2'length);

Convert from Std_Logic_Vector to Integer using Std_Logic_Arith

signal input_4   : std_logic_vector(3 downto 0);
signal output_4a : integer;
signal output_4b : integer;

-- Unsigned case
output_4a <= conv_integer(unsigned(input_4));

-- Signed case
output_4b <= conv_integer(signed(input_4));

Convert from Std_Logic_Vector to Signed using Std_Logic_Arith

signal input_6  : std_logic_vector(3 downto 0);
signal output_6 : signed(3 downto 0);

output_6 <= signed(input_6);

Convert from Std_Logic_Vector to Unsigned using Std_Logic_Arith

signal input_5  : std_logic_vector(3 downto 0);
signal output_5 : unsigned(3 downto 0);

output_5 <= unsigned(input_5);

Convert from Signed to Integer using Std_Logic_Arith

signal input_10  : signed(3 downto 0);
signal output_10 : integer;

output_10 <= conv_integer(input_10);

Convert from Signed to Std_Logic_Vector using Std_Logic_Arith

signal input_11  : signed(3 downto 0);
signal output_11 : std_logic_vector(3 downto 0);

output_11 <= std_logic_vector(input_11);

Convert from Signed to Unsigned using Std_Logic_Arith

signal input_12  : signed(3 downto 0);
signal output_12 : unsigned(3 downto 0);

output_12 <= unsigned(input_12);

Convert from Unsigned to Integer using Std_Logic_Arith

signal input_7  : unsigned(3 downto 0);
signal output_7 : integer;

output_7 <= conv_integer(input_7);

Convert from Unsigned to Signed using Std_Logic_Arith

signal input_9  : unsigned(3 downto 0);
signal output_9 : signed(3 downto 0);

output_9 <= signed(input_9);

Convert from Unsigned to Std_Logic_Vector using Std_Logic_Arith

signal input_8  : unsigned(3 downto 0);
signal output_8 : std_logic_vector(3 downto 0);

output_8 <= std_logic_vector(input_8);

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