Tracking ADC: Up/Down Counter for Fast, Continuous Signal Conversion

A third variation on the counter‑DAC based converter theme is, in my view, the most elegant. Instead of a conventional “up” counter driving the DAC, this design uses an up/down counter.

The counter runs continuously, and the up/down control line is driven by the comparator’s output. When the analog input exceeds the DAC output, the counter switches to count‑up mode. Conversely, if the DAC output is higher, it counts down. In either case the DAC output follows the input signal in real time.

Because the counter never resets, the binary output is updated on every clock pulse, eliminating the need for a shift register to latch the count at the end of a cycle.

One key benefit is speed: the converter can reach sampling rates of several MHz without the overhead of a reset phase.

As shown, the update time is far faster than other counting ADCs. At the beginning of the plot, when the counter must “catch up” to a sudden change in the analog signal, the rate of change matches that of the first counting ADC. The output ramps smoothly rather than jumping from zero, unlike counter‑ and successive‑approximation ADCs.

However, the binary output is never static; it toggles between counts on every clock pulse even with a perfectly stable input—a phenomenon known as bit bobble. This can be problematic for digital systems that expect a steady output.

Bit bobble can be mitigated by inserting a shift register that latches the counter output only when the value changes by two or more steps. Designing a detector for two consecutive counts in the same direction requires a bit of ingenuity but pays off.

RELATED WORKSHEET:

• Analog‑to‑Digital Conversion Worksheet